path: root/ir/be/riscv
Commit message (Collapse)AuthorAge
* riscv: support soft-float and the -march and -mabi switchesJohannes Bucher2019-11-29
* riscv: correctly lower aggregate parametersJohannes Bucher2019-11-08
| | | | | | | Function parameter aggregates are lowered according to the RISC-V ILP32 ABI. Consider that small structs are passed by value when lowering builtin va_arg
* riscv: lowering of builtin va_arg takes alignment rules into accountJohannes Bucher2019-11-08
* riscv: simplify frame pointer relative addressingJohannes Bucher2019-10-25
| | | | | Make use of the 'begin' parameter of be_layout_frame_types instead of fixing the offsets manually using a backend node flag.
* riscv: add support for variadic functionsJohannes Bucher2019-10-24
| | | | | | lowering of builtin va_arg still uses the be_default_lower_va_arg function which is not correct due to the alignment requirements of variadic arguments; a RISC-V specific implementation is needed
* riscv: add missing dump after lower_callsJohannes Bucher2019-06-25
* riscv: lower aggregate types at calls by replacing them with a pointer to ↵Johannes Bucher2019-06-19
| | | | the actual data
* riscv: add emit function for be_MemPerm nodesJohannes Bucher2019-06-19
| | | | | | uses a simple approach similar to the arm backend: save registers on the stack, load MemPerm ins in registers, write them back and restore the registers.
* riscv: add a peephole optimization for consecutive shift operationsJohannes Bucher2019-06-19
* riscv: support right shift for modes smaller than 32 bitJohannes Bucher2019-06-11
* riscv: rename register s0 -> fpJohannes Bucher2019-06-11
| | | | fp is an alternative ABI name for register s0
* riscv: fix function prologue + epilogueJohannes Bucher2019-06-11
* riscv: support frame pointer relative addressingJohannes Bucher2019-06-11
* riscv: support Alloc nodesJohannes Bucher2019-06-11
| | | | Introduced riscv backend nodes SubSP and SubSPimm for stack allocations
* riscv: support extension from mode Hu (16 bit) to machine sizeJohannes Bucher2019-05-17
* riscv: do not emit IncSP nodes with offset 0Johannes Bucher2019-05-17
* riscv: fix calculation of hi lo immediate (remove undefined behavior)Johannes Bucher2019-05-17
| | | | fixes runtime error in sanitize builds
* beasm: Tell the backends how to handle the fallthrough exec output of be_Asm.Christoph Mallon2019-04-05
* beasm: Handle operand modifier 'l' in all backends.Christoph Mallon2019-04-05
* beasm: Add BE_ASM_OPERAND_LABEL and tell the backends how to emit it.Christoph Mallon2019-04-05
* Remove unnecessary relative path from #include.Christoph Mallon2019-03-13
* riscv: fix invalid assembler errors due to too large immediatesJohannes Bucher2019-03-12
| | | | | | | | | | | RISC-V I-type and S-type instruction formats only accept 12 bit immediates as operands. Address offsets, constants, and IncSP values which exceed the 12 bit range are now correctly transformed into multiple instructions (lui + addi) The t0 register is now set to ignore, this allows building immediates using multiple instructions after register allocation.
* beasm: Factor out common code to add an immediate operand.Christoph Mallon2019-03-06
* Remove duplicate calls to be_set_asm_operand().Christoph Mallon2019-03-06
| | | | The callers of these functions do it, too.
* beasm: Support modifier 'c' (plain immediate) in all remaining backends.Christoph Mallon2019-03-06
| | | | These backends do not have a prefix for immediates anyway, so besides accepting the modifier there is nothing to do.
* fix mips and riscv function alignmentJohannes Bucher2019-03-06
* be: Factor out code to emit an unconditional jump in each backend.Christoph Mallon2019-03-04
* Silence compiler warnings.Andreas Fried2019-01-07
* riscv: Implement a basic RISC-V 32 backend.Christoph Mallon2018-08-15