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* Rename register FP to S0.Andreas Fried2021-04-06
| | | | | | S0 is the name preferred by GNU tools, and the only name accepted by the bare-metal assembler (riscv{32,64}-unknown-elf-as). This gives us less descriptive register names, but more portability.
* riscv: rename register s0 -> fpJohannes Bucher2019-06-11
| | | | fp is an alternative ABI name for register s0
* riscv: support Alloc nodesJohannes Bucher2019-06-11
| | | | Introduced riscv backend nodes SubSP and SubSPimm for stack allocations
* riscv: fix invalid assembler errors due to too large immediatesJohannes Bucher2019-03-12
| | | | | | | | | | | RISC-V I-type and S-type instruction formats only accept 12 bit immediates as operands. Address offsets, constants, and IncSP values which exceed the 12 bit range are now correctly transformed into multiple instructions (lui + addi) The t0 register is now set to ignore, this allows building immediates using multiple instructions after register allocation.
* riscv: Implement a basic RISC-V 32 backend.Christoph Mallon2018-08-15