| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Rename register FP to S0. | Andreas Fried | 2021-04-06 |
| * | riscv: rename register s0 -> fp | Johannes Bucher | 2019-06-11 |
| * | riscv: support Alloc nodes | Johannes Bucher | 2019-06-11 |
| * | riscv: fix invalid assembler errors due to too large immediates | Johannes Bucher | 2019-03-12 |
| * | riscv: Implement a basic RISC-V 32 backend. | Christoph Mallon | 2018-08-15 |
 |
index : libfirm | |
| Graph-Based Intermediate Representation | matthias.braun@kit.edu |
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