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path: root/ir/be/riscv/riscv_finish.c
Commit message (Collapse)AuthorAge
* riscv: add a peephole optimization for consecutive shift operationsJohannes Bucher2019-06-19
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* riscv: do not emit IncSP nodes with offset 0Johannes Bucher2019-05-17
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* Remove unnecessary relative path from #include.Christoph Mallon2019-03-13
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* riscv: fix invalid assembler errors due to too large immediatesJohannes Bucher2019-03-12
RISC-V I-type and S-type instruction formats only accept 12 bit immediates as operands. Address offsets, constants, and IncSP values which exceed the 12 bit range are now correctly transformed into multiple instructions (lui + addi) The t0 register is now set to ignore, this allows building immediates using multiple instructions after register allocation.