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* x86: add modern architecture variants and improve cpu detectionamd64-fmaJohannes Bucher2021-03-22
| | | | | | | | | | Added Intel and AMD x86 architecture variants up to Alder Lake and Zen3. The variants can be selected via the -march and -mtune backend options. Improved CPU architecture and feature detection for -march=native. All features defined in x86_architecture.h are now detected using cpuid. SIMD instruction extensions detection extended up to AVX2.
* ia32/amd64: split up architecture variant and cpu features into different ↵Johannes Bucher2021-03-22
| | | | | | | bitsets this allows to add support for more architecture variants and cpu features as the current bitset was nearly full
* add basic cpu architecture autodetection for amd64Johannes Bucher2021-03-22
| | | | | | | | | Existing code from the ia32 backend for cpuid autodetection is now used for both x86 backends. Similar to ia32, the -march and -mtune options are now available for amd64 (limited to 'generic' and 'native' atm) FMA3 support is now only available if the target machine supports it.
* amd64: support scalar fused-multiply-add instructions (FMA3)Johannes Bucher2021-03-22
| | | | | | | | | | Adds support for fused multiply-add of scalar double- and single-precision floating point values from the FMA3 instruction set. Comprises the instructions VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMADD132SS, VFMADD213SS, VFMADD231SS This feature can be enabled with the -mfma option.
* amd64: add pxor_0 instruction before cvtsi2sd to break dependency chainJohannes Bucher2020-02-21
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* amd64: peephole: remove consecutive zero extensionsJohannes Bucher2020-02-21
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* Fix handling of array-typed struct members in AMD64 ABI.Andreas Fried2019-11-08
| | | | | Arrays need to be considered for a slice even if their starting offset is outside the range in question (e.g. struct { long x[2]; };).
* beasm: Tell the backends how to handle the fallthrough exec output of be_Asm.Christoph Mallon2019-04-05
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* beasm: Handle operand modifier 'l' in all backends.Christoph Mallon2019-04-05
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* beasm: Add BE_ASM_OPERAND_LABEL and tell the backends how to emit it.Christoph Mallon2019-04-05
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* amd64: Also determine the frame offset for memory operands of be_Asm.Christoph Mallon2019-03-31
| | | | This fixes backend/asm_memory_access.c on amd64.
* amd64: Factor out code to determine the frame offset for an x86_addr_t.Christoph Mallon2019-03-31
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* amd64, ia32: Support all address modes in inline asm.Christoph Mallon2019-03-25
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* Zero out the result struct in x86_create_address_mode() instead of in each ↵Christoph Mallon2019-03-25
| | | | caller.
* Revert "amd64: emitter: assert that register should_be_same constraints are ↵Christoph Mallon2019-03-08
| | | | | | | | not violated" be_handle_2addr() has a generic checker. This reverts commit 12972986a79e5ab3df5e2d2ed8377c7db5d83754.
* beasm: Add helper function to check for occurrence of modifiers.Christoph Mallon2019-03-04
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* be: Factor out code to emit an unconditional jump in each backend.Christoph Mallon2019-03-04
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* improved readability/code quality according to clang-tidy readability checksJohannes Bucher2019-01-24
| | | | | | | resolved warnings for these checks: - readability-non-const-parameter - readability-avoid-const-params-in-decls - readability-named-parameter
* amd64 backend: add missing should_be_same constraints in builtin_ffsJohannes Bucher2019-01-11
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* amd64: emitter: assert that register should_be_same constraints are not violatedJohannes Bucher2019-01-11
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* Fixed conversion of signed 16 bit to floats in amd64 backendcpu2017Sebastian Graf2018-08-28
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* Fixed register constraints for hand-crafted xor node in gen_clzSebastian Graf2018-08-28
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* Fixed memory edges of ctz/bsfSebastian Graf2018-08-28
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* Directly use ${ARCH}_single_reg_req_${CLS}_${REG} instead of ↵Christoph Mallon2018-08-23
| | | | ${ARCH}_registers[REG_${REG}].single_req.
* be: Factor out code to get an input pos for a given register requirement.Christoph Mallon2018-08-23
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* Fix typos message and comment.Christoph Mallon2018-08-23
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* Remove the unused debug keys 'firm.be.amd64.cg' and 'firm.be.sparc.cg'.Christoph Mallon2018-08-19
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* amd64, mips, template: Mark nodes as fallthrough.Christoph Mallon2018-05-31
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* be: Factor out code to decide whether a basic block needs a label.Christoph Mallon2018-05-31
| | | | For this a new flag 'arch_irn_flag_fallthrough' is introduced to mark nodes which are capable of falling through to their successor.
* amd64: Remove stale TODO about lea.Christoph Mallon2018-05-22
| | | | This was handled in 694f67e45fc2d3f84bfa7036452484078252e378.
* Fix compiler errors if neither NDEBUG nor DEBUG_libfirm are definedSebastian Buchwald2018-05-16
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* be: Use a common struct to hold basic asm operand information.Christoph Mallon2018-05-08
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* amd64: Allow x87 registers as input even if clobbered.Christoph Mallon2018-05-04
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* amd64, ia32: Move each table of additional clobber names into the only file ↵Christoph Mallon2018-05-04
| | | | which uses it.
* be: Factor out parsing of register names for clobbers.Christoph Mallon2018-05-04
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* amd64, ia32: Support the asm operand modifier `P`.Christoph Mallon2018-04-15
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* amd64, ia32: Support the asm operand modifier `X`.Christoph Mallon2018-04-15
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* amd64, ia32: Support the asm operand modifier `p`.Christoph Mallon2018-04-15
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* amd64, ia32: Support the asm operand modifier `A`.Christoph Mallon2018-04-15
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* be: Handle '%u' centrally in BE_EMITF().Christoph Mallon2018-04-08
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* amd64, be, ia32, sparc: Record that there is a twice returning call (setjmp) ↵Christoph Mallon2018-04-03
| | | | | | centrally in the birg. This way not each backend has to keep a separate flag and also does not need to manually call be_forbid_coalescing().
* be, doc: '%%' is also handle by BE_EMITF().Christoph Mallon2018-04-03
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* be: Handle '%s' centrally in BE_EMITF().Christoph Mallon2018-04-02
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* be: Update documentation of what is handled by BE_EMITF().Christoph Mallon2018-04-02
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* amd64: Add peephole optimization `cmp $0, %r` -> `test %r, %r`.Christoph Mallon2018-03-20
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* be: Remove redundant "uses_memory".Christoph Mallon2018-03-06
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* amd64: Do not unnecessarily restrict flags requirements to the single register.Christoph Mallon2018-02-28
| | | | | Simply use the whole register class 'flags', which just contains the single register 'eflags'. Now all instructions consistently use 'flags'.
* be: Automatically use be_info_init_irn().Christoph Mallon2018-02-28
| | | | So far each backend had to call it manually.
* amd64, ia32: Remove redundant mode specifications from instructions.Christoph Mallon2018-02-28
| | | | the single out_req has the right mode.
* be: Turn the specification of each register class into a map.Christoph Mallon2018-02-26
| | | | | So far the mode and flags were in the last magic entry in each register class. Now they are entries in the map and the list of registers is also an entry.