Commit message (Expand)AuthorAge
* Rename and reformat compression requirement typeMaximilian Stemmer-Grabow2021-12-02
* Add metadata about different edge types to affinity graphMaximilian Stemmer-Grabow2021-12-02
* Use doubles instead of floats in copy minimization heuristicMaximilian Stemmer-Grabow2021-12-02
* riscv: Determine compression requirements for instructionsMaximilian Stemmer-Grabow2021-12-02
* Add affinity edges to account for instruction compresssion requirementsMaximilian Stemmer-Grabow2021-12-02
* Fix documentation commentMaximilian Stemmer-Grabow2021-12-02
* Relocate compression requirement check into its own fileMaximilian Stemmer-Grabow2021-12-02
* Add enum to represent basic instruction compression requirementsMaximilian Stemmer-Grabow2021-04-08
* Pass through compression requirement function ptr to copy optimizationMaximilian Stemmer-Grabow2021-04-07
* Fix missing field lost in git merge cleanupMaximilian Stemmer-Grabow2021-04-07
* Merge branch 'master' into regalloc-compressedMaximilian Stemmer-Grabow2021-04-07
| * Rename register FP to S0.Andreas Fried2021-04-06
| * x86: add modern architecture variants and improve cpu detectionamd64-fmaJohannes Bucher2021-03-22
| * ia32/amd64: split up architecture variant and cpu features into different bit...Johannes Bucher2021-03-22
| * add basic cpu architecture autodetection for amd64Johannes Bucher2021-03-22
| * amd64: support scalar fused-multiply-add instructions (FMA3)Johannes Bucher2021-03-22
| * be2addr: fix copy-after case for modes with mode_TJohannes Bucher2021-03-22
| * Recognize AArch64 as host cpu type.Manuel Mohr2021-03-04
| * Recognize quad precision floats as used on AArch64.Manuel Mohr2021-03-04
* | Add flag to indicate compressible registers to RISC-V specMaximilian Stemmer-Grabow2021-03-29
* | Reorder register declaration in RISC-V backendMaximilian Stemmer-Grabow2021-03-29
* Fix loop inversion where the header contains a data flow loop.Andreas Fried2020-07-30
* Always prefix variables in generated headers with "extern".Andreas Fried2020-06-16
* Make Makefile portable between make 4.2 and 4.3.Andreas Fried2020-04-29
* amd64: add pxor_0 instruction before cvtsi2sd to break dependency chainJohannes Bucher2020-02-21
* amd64: peephole: remove consecutive zero extensionsJohannes Bucher2020-02-21
* Extend loop unrolling: can now unroll nested loopJohannes Bucher2020-02-07
* remove debug graph dumps from LCSSA transformationJohannes Bucher2020-02-06
* execfreq: Only free DFS when we abort due to too large function.Andreas Fried2019-12-13
* Fix build scripts for MINGW environmentsJohannes Bucher2019-12-13
* default to -fPIC on OpenBSDJohannes Bucher2019-12-06
* riscv: support soft-float and the -march and -mabi switchesJohannes Bucher2019-11-29
* riscv: correctly lower aggregate parametersJohannes Bucher2019-11-08
* riscv: lowering of builtin va_arg takes alignment rules into accountJohannes Bucher2019-11-08
* Fix handling of array-typed struct members in AMD64 ABI.Andreas Fried2019-11-08
* riscv: simplify frame pointer relative addressingJohannes Bucher2019-10-25
* riscv: add support for variadic functionsJohannes Bucher2019-10-24
* store the index of the first variadic parameter in method typesJohannes Bucher2019-10-18
* Extend a + b == a + c → b == c to reference modesriscvSebastian Buchwald2019-08-09
* Set immediate kind for ia32_FldCWSebastian Buchwald2019-08-09
* riscv: add missing dump after lower_callsJohannes Bucher2019-06-25
* Place fewer Phis when constructing LCSSA form.better-lcssaAndreas Fried2019-06-19
* Only construct LCSSA Phis if control flow leaves a loop.Andreas Fried2019-06-19
* Add debugging output to LCSSA construction.Andreas Fried2019-06-19
* riscv: lower aggregate types at calls by replacing them with a pointer to the...Johannes Bucher2019-06-19
* riscv: add emit function for be_MemPerm nodesJohannes Bucher2019-06-19
* riscv: add a peephole optimization for consecutive shift operationsJohannes Bucher2019-06-19
* Add -g flag to cmake debug build flags.Andreas Fried2019-06-18
* lower_dw: implement a generic function for lowering Minus nodesJohannes Bucher2019-06-18
* riscv: support right shift for modes smaller than 32 bitJohannes Bucher2019-06-11