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* x86: add modern architecture variants and improve cpu detectionamd64-fmaJohannes Bucher2021-03-22
| | | | | | | | | | Added Intel and AMD x86 architecture variants up to Alder Lake and Zen3. The variants can be selected via the -march and -mtune backend options. Improved CPU architecture and feature detection for -march=native. All features defined in x86_architecture.h are now detected using cpuid. SIMD instruction extensions detection extended up to AVX2.
* ia32/amd64: split up architecture variant and cpu features into different ↵Johannes Bucher2021-03-22
| | | | | | | bitsets this allows to add support for more architecture variants and cpu features as the current bitset was nearly full
* add basic cpu architecture autodetection for amd64Johannes Bucher2021-03-22
| | | | | | | | | Existing code from the ia32 backend for cpuid autodetection is now used for both x86 backends. Similar to ia32, the -march and -mtune options are now available for amd64 (limited to 'generic' and 'native' atm) FMA3 support is now only available if the target machine supports it.
* amd64: support scalar fused-multiply-add instructions (FMA3)Johannes Bucher2021-03-22
| | | | | | | | | | Adds support for fused multiply-add of scalar double- and single-precision floating point values from the FMA3 instruction set. Comprises the instructions VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMADD132SS, VFMADD213SS, VFMADD231SS This feature can be enabled with the -mfma option.
* be2addr: fix copy-after case for modes with mode_TJohannes Bucher2021-03-22
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* Recognize AArch64 as host cpu type.Manuel Mohr2021-03-04
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* Recognize quad precision floats as used on AArch64.Manuel Mohr2021-03-04
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* Fix loop inversion where the header contains a data flow loop.Andreas Fried2020-07-30
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* Always prefix variables in generated headers with "extern".Andreas Fried2020-06-16
| | | | | Since GCC 10, the linker no longer accepts multiple definitions of the same variable. We therefore always need to mark the ones in nodes.h as extern.
* Make Makefile portable between make 4.2 and 4.3.Andreas Fried2020-04-29
| | | | | See https://lists.gnu.org/archive/html/bug-make/2020-01/msg00057.html for an explanation and the recommended workaround.
* amd64: add pxor_0 instruction before cvtsi2sd to break dependency chainJohannes Bucher2020-02-21
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* amd64: peephole: remove consecutive zero extensionsJohannes Bucher2020-02-21
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* Extend loop unrolling: can now unroll nested loopJohannes Bucher2020-02-07
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* remove debug graph dumps from LCSSA transformationJohannes Bucher2020-02-06
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* execfreq: Only free DFS when we abort due to too large function.Andreas Fried2019-12-13
| | | | By this point, the IR resources have not been allocated yet.
* Fix build scripts for MINGW environmentsJohannes Bucher2019-12-13
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* default to -fPIC on OpenBSDJohannes Bucher2019-12-06
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* riscv: support soft-float and the -march and -mabi switchesJohannes Bucher2019-11-29
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* riscv: correctly lower aggregate parametersJohannes Bucher2019-11-08
| | | | | | | Function parameter aggregates are lowered according to the RISC-V ILP32 ABI. Consider that small structs are passed by value when lowering builtin va_arg
* riscv: lowering of builtin va_arg takes alignment rules into accountJohannes Bucher2019-11-08
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* Fix handling of array-typed struct members in AMD64 ABI.Andreas Fried2019-11-08
| | | | | Arrays need to be considered for a slice even if their starting offset is outside the range in question (e.g. struct { long x[2]; };).
* riscv: simplify frame pointer relative addressingJohannes Bucher2019-10-25
| | | | | Make use of the 'begin' parameter of be_layout_frame_types instead of fixing the offsets manually using a backend node flag.
* riscv: add support for variadic functionsJohannes Bucher2019-10-24
| | | | | | lowering of builtin va_arg still uses the be_default_lower_va_arg function which is not correct due to the alignment requirements of variadic arguments; a RISC-V specific implementation is needed
* store the index of the first variadic parameter in method typesJohannes Bucher2019-10-18
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* Extend a + b == a + c → b == c to reference modesriscvSebastian Buchwald2019-08-09
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* Set immediate kind for ia32_FldCWSebastian Buchwald2019-08-09
| | | | This fixes x86code/float2int.c.
* riscv: add missing dump after lower_callsJohannes Bucher2019-06-25
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* Place fewer Phis when constructing LCSSA form.better-lcssaAndreas Fried2019-06-19
| | | | | | | | This implementation probably places the minimal amount of Phis for reducible control flow, but will miss SCCs. It uses the following rules: - If the block has one predecessor, pass along the predecessor's Phi. - If all predecessors are the same Phi or a self-loop, use the predecessor.
* Only construct LCSSA Phis if control flow leaves a loop.Andreas Fried2019-06-19
| | | | Otherwise, there is no place where an LCSSA Phi needs to go.
* Add debugging output to LCSSA construction.Andreas Fried2019-06-19
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* riscv: lower aggregate types at calls by replacing them with a pointer to ↵Johannes Bucher2019-06-19
| | | | the actual data
* riscv: add emit function for be_MemPerm nodesJohannes Bucher2019-06-19
| | | | | | uses a simple approach similar to the arm backend: save registers on the stack, load MemPerm ins in registers, write them back and restore the registers.
* riscv: add a peephole optimization for consecutive shift operationsJohannes Bucher2019-06-19
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* Add -g flag to cmake debug build flags.Andreas Fried2019-06-18
| | | | Apparently the implicit -g is lost when setting -DDEBUG_libfirm.
* lower_dw: implement a generic function for lowering Minus nodesJohannes Bucher2019-06-18
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* riscv: support right shift for modes smaller than 32 bitJohannes Bucher2019-06-11
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* riscv: rename register s0 -> fpJohannes Bucher2019-06-11
| | | | fp is an alternative ABI name for register s0
* riscv: fix function prologue + epilogueJohannes Bucher2019-06-11
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* riscv: support frame pointer relative addressingJohannes Bucher2019-06-11
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* riscv: support Alloc nodesJohannes Bucher2019-06-11
| | | | Introduced riscv backend nodes SubSP and SubSPimm for stack allocations
* Remove nonexistent @see.Andreas Fried2019-06-11
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* Add more documentation for add_irg_properties and clear_irg_properties.Andreas Fried2019-06-11
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* Reorder functions to keep irg_properties-related stuff together.Andreas Fried2019-06-11
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* Set DEBUG_libfirm for CMake debug builds.Andreas Fried2019-05-24
| | | | | | In order to build libfirm with debugging enabled, use cmake -DCMAKE_BUILD_TYPE=Debug. It also works if you build cparser, cmake will pass the option along.
* Prevent direct inclusion of the generated nodes.h.Christoph Mallon2019-05-17
| | | | This fixes #14.
* riscv: support extension from mode Hu (16 bit) to machine sizeJohannes Bucher2019-05-17
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* riscv: do not emit IncSP nodes with offset 0Johannes Bucher2019-05-17
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* riscv: fix calculation of hi lo immediate (remove undefined behavior)Johannes Bucher2019-05-17
| | | | fixes runtime error in sanitize builds
* add a missing includeBasile-z2019-04-26
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* Add include for size_tSebastian Buchwald2019-04-26
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