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authorChristoph Mallon <christoph.mallon@gmx.de>2018-03-31 12:12:43 +0200
committerChristoph Mallon <christoph.mallon@gmx.de>2018-08-15 12:05:18 +0200
commitb031096c75829e287eb18942542ebcd4c6daa8a9 (patch)
tree5e27a38e506a6c4cfe3ff3e3f0513fb79866b36f /ir/be/target.c
parentd87cbba82fd6596a233f3bf2910d1eaa80f23bb5 (diff)
riscv: Implement a basic RISC-V 32 backend.
Diffstat (limited to 'ir/be/target.c')
-rw-r--r--ir/be/target.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/ir/be/target.c b/ir/be/target.c
index 62cb06c..12e1d70 100644
--- a/ir/be/target.c
+++ b/ir/be/target.c
@@ -37,6 +37,8 @@ int ir_target_set_triple(ir_machine_triple_t const *machine)
isa = &amd64_isa_if;
} else if (streq(cpu, "mips")) {
isa = &mips_isa_if;
+ } else if (streq(cpu, "riscv32")) {
+ isa = &riscv32_isa_if;
} else if (streq(cpu, "TEMPLATE")) {
isa = &TEMPLATE_isa_if;
} else {