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authorAndreas Fried <andreas.fried@kit.edu>2021-04-01 15:33:21 +0200
committerAndreas Fried <andreas.fried@kit.edu>2021-04-06 15:33:42 +0200
commit6dfeab4016d89fb2546d7772d52b84facdcb0f7b (patch)
tree42ca9aac28f163edf272d59407e62c7f973fa8b1 /ir/be/riscv/riscv_spec.pl
parentfa10c7c7db0b1d57220a0d55fe8bbecce751f794 (diff)
Rename register FP to S0.
S0 is the name preferred by GNU tools, and the only name accepted by the bare-metal assembler (riscv{32,64}-unknown-elf-as). This gives us less descriptive register names, but more portability.
Diffstat (limited to 'ir/be/riscv/riscv_spec.pl')
-rw-r--r--ir/be/riscv/riscv_spec.pl2
1 files changed, 1 insertions, 1 deletions
diff --git a/ir/be/riscv/riscv_spec.pl b/ir/be/riscv/riscv_spec.pl
index 6e1a92b..1a0ff7d 100644
--- a/ir/be/riscv/riscv_spec.pl
+++ b/ir/be/riscv/riscv_spec.pl
@@ -17,7 +17,7 @@ my $mode_gp = "mode_Iu";
{ name => "t0", encoding => 5 },
{ name => "t1", encoding => 6 },
{ name => "t2", encoding => 7 },
- { name => "fp", encoding => 8 },
+ { name => "s0", encoding => 8 },
{ name => "s1", encoding => 9 },
{ name => "a0", encoding => 10 },
{ name => "a1", encoding => 11 },