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authorJohannes Bucher <johannes.bucher2@student.kit.edu>2019-03-06 16:19:07 +0100
committerJohannes Bucher <johannes.bucher2@student.kit.edu>2019-03-12 10:01:09 +0100
commit02952f4342b2ffa40ba33292770416625ea77681 (patch)
tree5f1b4a9522f1808950f1ed3c0bbaf2aa5968db39 /ir/be/riscv/riscv_spec.pl
parent9f4c8ce4103b25dc949f46a9020264bbcfd5f97f (diff)
riscv: fix invalid assembler errors due to too large immediates
RISC-V I-type and S-type instruction formats only accept 12 bit immediates as operands. Address offsets, constants, and IncSP values which exceed the 12 bit range are now correctly transformed into multiple instructions (lui + addi) The t0 register is now set to ignore, this allows building immediates using multiple instructions after register allocation.
Diffstat (limited to 'ir/be/riscv/riscv_spec.pl')
-rw-r--r--ir/be/riscv/riscv_spec.pl10
1 files changed, 10 insertions, 0 deletions
diff --git a/ir/be/riscv/riscv_spec.pl b/ir/be/riscv/riscv_spec.pl
index 1488eaf..b36af18 100644
--- a/ir/be/riscv/riscv_spec.pl
+++ b/ir/be/riscv/riscv_spec.pl
@@ -237,4 +237,14 @@ xor => { template => $binOp },
xori => { template => $immediateOp },
+FrameAddr => {
+ op_flags => [ "constlike" ],
+ irn_flags => [ "rematerializable" ],
+ attr => "ir_entity *ent, int32_t val",
+ in_reqs => [ "cls-gp" ],
+ out_reqs => [ "cls-gp" ],
+ ins => [ "base" ],
+ attr_type => "riscv_immediate_attr_t",
+},
+
);