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authorMatthias Braun <matze@braunis.de>2011-08-15 13:41:11 +0200
committerMatthias Braun <matze@braunis.de>2011-08-15 14:03:03 +0200
commit41dc42afc8d00e0f364711ed0c919e4e29cb20e4 (patch)
tree89b7e8ab7e295f9fcfe18a40bfb001b91c4e5f34 /ir/be/bespill.c
parented7cc1daadbdd28b5550157080dcbbbea348c097 (diff)
big refactoring of arch_XXX functions
This tries to get the names in a consistent format. We basically have 2 views on register allocation/constraints now: 1) Register Requirements and Assigments are per-instruction. Each instruction has requirements on its inputs and outputs, register get assigned for outputs of an instruction (assignment is an attribute of an instruction, not of the Proj-nodes). The internal datastructures model this form! The functions here have the form: arch_get_irn_register_req_in(node, input_nr) arch_get_irn_register_in(node, input_nr) arch_get_irn_register_req_out(node, output_nr) arch_set_irn_register_out(node, output_nr, register) 2) Register Requirements and Assignments are on firm-values. This view allows to query/assign requirements and registers at the Proj nodes instead of the repsective predecessors. This is a convenience interface modeled on top of the other! The functions have the form: arch_get_irn_register_req(node) arch_get_irn_register(node) arch_set_irn_register(node, register)
Diffstat (limited to 'ir/be/bespill.c')
-rw-r--r--ir/be/bespill.c34
1 files changed, 11 insertions, 23 deletions
diff --git a/ir/be/bespill.c b/ir/be/bespill.c
index cf2985d..c83653a 100644
--- a/ir/be/bespill.c
+++ b/ir/be/bespill.c
@@ -64,6 +64,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node)
unsigned *tmp = NULL;
unsigned *def_constr = NULL;
int arity = get_irn_arity(node);
+ ir_node *def;
int i, i2;
@@ -75,7 +76,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node)
*/
for (i = 0; i < arity; ++i) {
ir_node *op = get_irn_n(node, i);
- const arch_register_req_t *req = arch_get_register_req(node, i);
+ const arch_register_req_t *req = arch_get_irn_register_req_in(node, i);
const arch_register_t *reg;
ir_node *copy;
@@ -110,7 +111,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node)
ir_node *copy;
const arch_register_req_t *req;
- req = arch_get_register_req(node, i);
+ req = arch_get_irn_register_req_in(node, i);
if (req->cls != cls)
continue;
@@ -125,7 +126,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node)
ir_node *in2;
const arch_register_req_t *req2;
- req2 = arch_get_register_req(node, i2);
+ req2 = arch_get_irn_register_req_in(node, i2);
if (req2->cls != cls)
continue;
if (! (req2->type & arch_register_req_type_limited))
@@ -152,27 +153,14 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node)
}
/* collect all registers occurring in out constraints. */
- if (get_irn_mode(node) == mode_T) {
- const ir_edge_t *edge;
-
- foreach_out_edge(node, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- const arch_register_req_t *req = arch_get_register_req_out(proj);
- if (! (req->type & arch_register_req_type_limited))
- continue;
-
- if (def_constr == NULL) {
- rbitset_alloca(def_constr, cls->n_regs);
- }
- rbitset_or(def_constr, req->limited, cls->n_regs);
- }
- } else {
- const arch_register_req_t *req = arch_get_register_req_out(node);
- if (req->type & arch_register_req_type_limited) {
+ be_foreach_definition(node, cls, def,
+ if (! (req_->type & arch_register_req_type_limited))
+ continue;
+ if (def_constr == NULL) {
rbitset_alloca(def_constr, cls->n_regs);
- rbitset_or(def_constr, req->limited, cls->n_regs);
}
- }
+ rbitset_or(def_constr, req_->limited, cls->n_regs);
+ );
/* no output constraints => we're good */
if (def_constr == NULL) {
@@ -195,7 +183,7 @@ static void prepare_constr_insn(be_pre_spill_env_t *env, ir_node *node)
* 2) lives through the node.
* 3) is constrained to a register occurring in out constraints.
*/
- req = arch_get_register_req(node, i);
+ req = arch_get_irn_register_req_in(node, i);
if (req->cls != cls)
continue;
if (!(req->type & arch_register_req_type_limited))