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authorMatthias Braun <matze@braunis.de>2014-07-07 16:03:07 +0200
committerMatthias Braun <matze@braunis.de>2014-07-07 16:06:29 +0200
commit9d0b843b08f4ef4360f682427b51bc0cccb36092 (patch)
tree38fc0ad411cf36e1ecde668d40400a10a21def82 /ir/be/beprefalloc.c
parent771728a99730d7fbb660d4108dd818792f52b81f (diff)
be: change pre spill prepare phase to work on all register classes at once
- Only iterating over the graph once should be slightly faster - We don't need to insert the middle of register allocation logic but can perform it once before. - We can gather statistics on the prepared graph before spilling/regalloc has happened.
Diffstat (limited to 'ir/be/beprefalloc.c')
-rw-r--r--ir/be/beprefalloc.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/ir/be/beprefalloc.c b/ir/be/beprefalloc.c
index 6f96b97..6a6fe7d 100644
--- a/ir/be/beprefalloc.c
+++ b/ir/be/beprefalloc.c
@@ -1801,13 +1801,6 @@ static void dump(int mask, ir_graph *irg, const char *suffix)
*/
static void spill(void)
{
- /* make sure all nodes show their real register pressure */
- be_timer_push(T_RA_CONSTR);
- be_pre_spill_prepare_constr(irg, cls);
- be_timer_pop(T_RA_CONSTR);
-
- dump(DUMP_RA, irg, "spillprepare");
-
/* spill */
be_timer_push(T_RA_SPILL);
be_do_spill(irg, cls);