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authorChristoph Mallon <christoph.mallon@gmx.de>2019-03-22 23:37:49 +0100
committerChristoph Mallon <christoph.mallon@gmx.de>2019-03-24 08:13:29 +0100
commitf6e223b6d1711cc4e58d0248f5b22a3d5cc79fd2 (patch)
tree1d70c1a3f871ef47d08baa2280bf7ac1b8e729ea /ir/be/beasm.c
parent3569ffd30ee6608a0f8466415600c57d4c6102a7 (diff)
be: Refine modelling of additional register pressure.
Now additional pressure is applied to the register pressure either before (positive value) or after (negative value) the instruction. So far the value was applied to both the register pressure before and after the instruction. This leads to overapproximation, e.g. for cltd (in: eax, out: edx). When the input lives through then the register pressure after the instruction is 2, but +1 additional pressure unnecessarily increases it to 3. Now the additional pressure is applied to either the register pressure before or after the instruction. For cltd applying it only before the instruction is optimal, because the output can never be paired with the input. Typical symptom was overspilling around cltd+idiv. This still can overapproximate the actual register demand when in/out pairing depends on whether an input lives through. E.g. in: eax+reg, out: edx. Then 3 registers are needed when the reg input lives through. (additional pressure before 1) But only 2 registers are needed when the reg input dies. (no additional pressure) This fixes lit/overspill_cltd.c.
Diffstat (limited to 'ir/be/beasm.c')
-rw-r--r--ir/be/beasm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/ir/be/beasm.c b/ir/be/beasm.c
index c13a458..150f238 100644
--- a/ir/be/beasm.c
+++ b/ir/be/beasm.c
@@ -324,7 +324,7 @@ ir_node *be_make_asm(ir_node const *const node, be_asm_info_t const *const info,
if (!inreq->cls->manual_ra) {
assert(inreq->cls->index < ARRAY_SIZE(add_pressure));
if (!match_requirement(out_reqs, n_outs, used_outs, inreq))
- add_pressure[inreq->cls->index]++;
+ add_pressure[inreq->cls->index]--;
}
}
}