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authorChristoph Mallon <christoph.mallon@gmx.de>2018-05-04 06:45:05 +0200
committerSebastian Buchwald <Sebastian.Buchwald@kit.edu>2018-05-04 22:47:07 +0200
commit11579d197df0c891d815de563055831c696b8164 (patch)
tree54a66d7d80babf770e2a8c401d60415c483deb00 /ir/be/amd64
parent9b7b69480d36584826a3621b5cf99b96bd1d08d8 (diff)
amd64, ia32: Move each table of additional clobber names into the only file which uses it.
Diffstat (limited to 'ir/be/amd64')
-rw-r--r--ir/be/amd64/amd64_bearch.c22
-rw-r--r--ir/be/amd64/amd64_transform.c22
-rw-r--r--ir/be/amd64/amd64_transform.h1
3 files changed, 22 insertions, 23 deletions
diff --git a/ir/be/amd64/amd64_bearch.c b/ir/be/amd64/amd64_bearch.c
index 6915242..0d15256 100644
--- a/ir/be/amd64/amd64_bearch.c
+++ b/ir/be/amd64/amd64_bearch.c
@@ -785,6 +785,28 @@ static unsigned amd64_get_op_estimated_cost(const ir_node *node)
return 1;
}
+/** we don't have a concept of aliasing registers, so enumerate them
+ * manually for the asm nodes. */
+static be_register_name_t const amd64_additional_reg_names[] = {
+ { "al", REG_RAX }, { "ah", REG_RAX }, { "ax", REG_RAX }, { "eax", REG_RAX },
+ { "bl", REG_RBX }, { "bh", REG_RBX }, { "bx", REG_RBX }, { "ebx", REG_RBX },
+ { "cl", REG_RCX }, { "ch", REG_RCX }, { "cx", REG_RCX }, { "ecx", REG_RCX },
+ { "dl", REG_RDX }, { "dh", REG_RDX }, { "dx", REG_RDX }, { "edx", REG_RDX },
+ { "sil", REG_RSI }, { "si", REG_RSI }, { "esi", REG_RSI },
+ { "dil", REG_RDI }, { "di", REG_RDI }, { "edi", REG_RDI },
+ { "bpl", REG_RBP }, { "bp", REG_RBP }, { "ebp", REG_RBP },
+ { "spl", REG_RSP }, { "sp", REG_RSP }, { "esp", REG_RSP },
+ { "r8b", REG_R8 }, { "r8w", REG_R8 }, { "r8d", REG_R8 },
+ { "r9b", REG_R9 }, { "r9w", REG_R9 }, { "r9d", REG_R9 },
+ { "r10b", REG_R10 }, { "r10w", REG_R10 }, { "r10d", REG_R10 },
+ { "r11b", REG_R11 }, { "r11w", REG_R11 }, { "r11d", REG_R11 },
+ { "r12b", REG_R12 }, { "r12w", REG_R12 }, { "r12d", REG_R12 },
+ { "r13b", REG_R13 }, { "r13w", REG_R13 }, { "r13d", REG_R13 },
+ { "r14b", REG_R14 }, { "r14w", REG_R14 }, { "r14d", REG_R14 },
+ { "r15b", REG_R15 }, { "r15w", REG_R15 }, { "r15d", REG_R15 },
+ { NULL, ~0u }
+};
+
arch_isa_if_t const amd64_isa_if = {
.name = "amd64",
.pointer_size = 8,
diff --git a/ir/be/amd64/amd64_transform.c b/ir/be/amd64/amd64_transform.c
index d1094df..df5c429 100644
--- a/ir/be/amd64/amd64_transform.c
+++ b/ir/be/amd64/amd64_transform.c
@@ -40,28 +40,6 @@ DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static x86_cconv_t *current_cconv = NULL;
static be_stack_env_t stack_env;
-/** we don't have a concept of aliasing registers, so enumerate them
- * manually for the asm nodes. */
-be_register_name_t const amd64_additional_reg_names[] = {
- { "al", REG_RAX }, { "ah", REG_RAX }, { "ax", REG_RAX }, { "eax", REG_RAX },
- { "bl", REG_RBX }, { "bh", REG_RBX }, { "bx", REG_RBX }, { "ebx", REG_RBX },
- { "cl", REG_RCX }, { "ch", REG_RCX }, { "cx", REG_RCX }, { "ecx", REG_RCX },
- { "dl", REG_RDX }, { "dh", REG_RDX }, { "dx", REG_RDX }, { "edx", REG_RDX },
- { "sil", REG_RSI }, { "si", REG_RSI }, { "esi", REG_RSI },
- { "dil", REG_RDI }, { "di", REG_RDI }, { "edi", REG_RDI },
- { "bpl", REG_RBP }, { "bp", REG_RBP }, { "ebp", REG_RBP },
- { "spl", REG_RSP }, { "sp", REG_RSP }, { "esp", REG_RSP },
- { "r8b", REG_R8 }, { "r8w", REG_R8 }, { "r8d", REG_R8 },
- { "r9b", REG_R9 }, { "r9w", REG_R9 }, { "r9d", REG_R9 },
- { "r10b", REG_R10 }, { "r10w", REG_R10 }, { "r10d", REG_R10 },
- { "r11b", REG_R11 }, { "r11w", REG_R11 }, { "r11d", REG_R11 },
- { "r12b", REG_R12 }, { "r12w", REG_R12 }, { "r12d", REG_R12 },
- { "r13b", REG_R13 }, { "r13w", REG_R13 }, { "r13d", REG_R13 },
- { "r14b", REG_R14 }, { "r14w", REG_R14 }, { "r14d", REG_R14 },
- { "r15b", REG_R15 }, { "r15w", REG_R15 }, { "r15d", REG_R15 },
- { NULL, ~0u }
-};
-
#define GP &amd64_reg_classes[CLASS_amd64_gp]
const x86_asm_constraint_list_t amd64_asm_constraints = {
['A'] = { MATCH_REG, GP, 1 << REG_GP_RAX | 1 << REG_GP_RDX },
diff --git a/ir/be/amd64/amd64_transform.h b/ir/be/amd64/amd64_transform.h
index 2acad3e..36227ba 100644
--- a/ir/be/amd64/amd64_transform.h
+++ b/ir/be/amd64/amd64_transform.h
@@ -14,7 +14,6 @@
#include "x86_address_mode.h"
#include "x86_asm.h"
-extern const be_register_name_t amd64_additional_reg_names[];
extern const x86_asm_constraint_list_t amd64_asm_constraints;
extern arch_register_req_t const amd64_requirement_gp_same_0;