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authorChristoph Mallon <christoph.mallon@gmx.de>2019-03-06 23:18:04 +0100
committerChristoph Mallon <christoph.mallon@gmx.de>2019-03-06 23:19:28 +0100
commit23496a80af29a067e0f65a4a4d3c1075f1772a3a (patch)
treeace42a67799324ac300d98cb4b192a9bbfec09cd
parenta08346ccb0d3aa7063dfed2197621880c1a6bf7a (diff)
beasm: Factor out common code to add an immediate operand.
-rw-r--r--ir/be/arm/arm_transform.c2
-rw-r--r--ir/be/beasm.h5
-rw-r--r--ir/be/ia32/x86_asm.c2
-rw-r--r--ir/be/mips/mips_transform.c2
-rw-r--r--ir/be/riscv/riscv_transform.c2
-rw-r--r--ir/be/sparc/sparc_transform.c2
6 files changed, 10 insertions, 5 deletions
diff --git a/ir/be/arm/arm_transform.c b/ir/be/arm/arm_transform.c
index d246c5b..a492d86 100644
--- a/ir/be/arm/arm_transform.c
+++ b/ir/be/arm/arm_transform.c
@@ -2020,7 +2020,7 @@ static ir_node *gen_ASM(ir_node *const node)
ir_node *const in = get_ASM_input(node, in_pos);
char const imm = be_constraint.immediate_type;
if (imm != '\0' && arm_match_immediate(op, in, imm)) {
- be_set_asm_operand(&op->op, BE_ASM_OPERAND_IMMEDIATE, -1);
+ be_asm_add_immediate(&op->op);
} else if (be_constraint.same_as >= 0) {
int const out_pos = operands[be_constraint.same_as].op.pos;
arch_register_req_t const *const ireq = info.out_reqs[out_pos];
diff --git a/ir/be/beasm.h b/ir/be/beasm.h
index 2af6154..d7fe333 100644
--- a/ir/be/beasm.h
+++ b/ir/be/beasm.h
@@ -40,6 +40,11 @@ static inline void be_set_asm_operand(be_asm_operand_t* const op, be_asm_operand
op->pos = pos;
}
+static inline void be_asm_add_immediate(be_asm_operand_t *const op)
+{
+ be_set_asm_operand(op, BE_ASM_OPERAND_IMMEDIATE, -1);
+}
+
/**
* An assembler constraint.
*/
diff --git a/ir/be/ia32/x86_asm.c b/ir/be/ia32/x86_asm.c
index 69fd5a3..1f0fda6 100644
--- a/ir/be/ia32/x86_asm.c
+++ b/ir/be/ia32/x86_asm.c
@@ -86,7 +86,7 @@ ir_node *x86_match_ASM(ir_node const *const node, x86_asm_constraint_list_t cons
ir_node *const in = get_ASM_input(node, in_pos);
char const imm = be_constraint.immediate_type;
if (imm != '\0' && x86_match_immediate(&op->u.imm32, in, imm)) {
- be_set_asm_operand(&op->op, BE_ASM_OPERAND_IMMEDIATE, -1);
+ be_asm_add_immediate(&op->op);
} else if (be_constraint.same_as >= 0) {
int const out_pos = operands[be_constraint.same_as].op.pos;
arch_register_req_t const *const ireq = info.out_reqs[out_pos];
diff --git a/ir/be/mips/mips_transform.c b/ir/be/mips/mips_transform.c
index cce8f7e..974036b 100644
--- a/ir/be/mips/mips_transform.c
+++ b/ir/be/mips/mips_transform.c
@@ -272,7 +272,7 @@ static ir_node *gen_ASM(ir_node *const node)
ir_node *const in = get_ASM_input(node, in_pos);
char const imm = be_constraint.immediate_type;
if (imm != '\0' && mips_match_immediate(op, in, imm)) {
- be_set_asm_operand(&op->op, BE_ASM_OPERAND_IMMEDIATE, -1);
+ be_asm_add_immediate(&op->op);
} else if (be_constraint.same_as >= 0) {
int const out_pos = operands[be_constraint.same_as].op.pos;
arch_register_req_t const *const ireq = info.out_reqs[out_pos];
diff --git a/ir/be/riscv/riscv_transform.c b/ir/be/riscv/riscv_transform.c
index 4a3fae6..847f79e 100644
--- a/ir/be/riscv/riscv_transform.c
+++ b/ir/be/riscv/riscv_transform.c
@@ -241,7 +241,7 @@ static ir_node *gen_ASM(ir_node *const node)
ir_node *const in = get_ASM_input(node, in_pos);
char const imm = be_constraint.immediate_type;
if (imm != '\0' && riscv_match_immediate(op, in, imm)) {
- be_set_asm_operand(&op->op, BE_ASM_OPERAND_IMMEDIATE, -1);
+ be_asm_add_immediate(&op->op);
} else if (be_constraint.same_as >= 0) {
int const out_pos = operands[be_constraint.same_as].op.pos;
arch_register_req_t const *const ireq = info.out_reqs[out_pos];
diff --git a/ir/be/sparc/sparc_transform.c b/ir/be/sparc/sparc_transform.c
index 75b99ee..1895ba6 100644
--- a/ir/be/sparc/sparc_transform.c
+++ b/ir/be/sparc/sparc_transform.c
@@ -283,7 +283,7 @@ static ir_node *gen_ASM(ir_node *node)
ir_node *const in = get_ASM_input(node, in_pos);
char const imm = be_constraint.immediate_type;
if (imm != '\0' && sparc_match_immediate(op, in, imm)) {
- be_set_asm_operand(&op->op, BE_ASM_OPERAND_IMMEDIATE, -1);
+ be_asm_add_immediate(&op->op);
} else if (be_constraint.same_as >= 0) {
int const out_pos = operands[be_constraint.same_as].op.pos;
arch_register_req_t const *const ireq = info.out_reqs[out_pos];