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authorAndreas Fried <andreas.fried@kit.edu>2022-03-25 18:14:20 +0100
committerAndreas Fried <andreas.fried@kit.edu>2022-03-25 18:14:20 +0100
commitb528aa4a7cb4d77bb193479e430a036cb0e6ac98 (patch)
tree32ab67a9e220091cc71b72a5f4844cdc6e20deac
parent6220c33fed5bcb924f3bb91dec878d2a063cb06f (diff)
riscv_transform: Use correct bit width for Proj_Proj_Start.riscv64
-rw-r--r--ir/be/riscv/riscv_transform.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/ir/be/riscv/riscv_transform.c b/ir/be/riscv/riscv_transform.c
index a0bd0aa..8aeee86 100644
--- a/ir/be/riscv/riscv_transform.c
+++ b/ir/be/riscv/riscv_transform.c
@@ -1049,7 +1049,9 @@ static ir_node *gen_Proj_Proj_Start(ir_node *const node)
ir_node *const block = be_transform_nodes_block(node);
ir_node *const mem = be_get_Start_mem(irg);
ir_node *const base = cur_cconv.omit_fp ? get_Start_sp(irg) : get_Start_fp(irg);
- ir_node *const load = new_bd_riscv_lw(dbgi, block, mem, base, param->entity, 0);
+ ir_node *const load = riscv_is_64() ?
+ new_bd_riscv_ld(dbgi, block, mem, base, param->entity, 0) :
+ new_bd_riscv_lw(dbgi, block, mem, base, param->entity, 0);
return be_new_Proj(load, pn_riscv_lw_res);
}
}