summaryrefslogtreecommitdiffhomepage
diff options
context:
space:
mode:
authorAndreas Fried <andreas.fried@kit.edu>2021-11-19 16:53:42 +0100
committerAndreas Fried <andreas.fried@kit.edu>2021-12-02 12:57:28 +0100
commit6860f3c75cbb4af7ed8e482f25ecf973608c166d (patch)
tree5e183f4e2b5ac22dc31dc336300073e546b60c39
parent540d72365c2d488df1e895d3de0c25b205e6b423 (diff)
Fix generation of MemPerm with new register order.
Since now sp comes at index 13, we can only start there and need to further restrict the arity of the MemPerm.
-rw-r--r--ir/be/riscv/riscv_emitter.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/ir/be/riscv/riscv_emitter.c b/ir/be/riscv/riscv_emitter.c
index 2f2ab0e..02fb44f 100644
--- a/ir/be/riscv/riscv_emitter.c
+++ b/ir/be/riscv/riscv_emitter.c
@@ -217,7 +217,7 @@ static void emit_be_MemPerm(ir_node const *const node)
bool const omit_fp = riscv_get_irg_data(get_irn_irg(node))->omit_fp;
int const memperm_arity = be_get_MemPerm_entity_arity(node);
- int const max_arity = 23;
+ int const max_arity = 19;
if (memperm_arity > max_arity)
panic("memperm with more than %d inputs not supported yet", max_arity);
@@ -229,7 +229,7 @@ static void emit_be_MemPerm(ir_node const *const node)
riscv_emitf(node, "addi\tsp, sp, -%d", memperm_arity * RISCV_REGISTER_SIZE);
for (int i = 0; i < memperm_arity; ++i) {
/* spill register */
- arch_register_t const *const reg = arch_register_for_index(&riscv_reg_classes[CLASS_riscv_gp], i + 9);
+ arch_register_t const *const reg = arch_register_for_index(&riscv_reg_classes[CLASS_riscv_gp], i + 13);
riscv_emitf(node, "sw\t%s, %d(sp)", reg->name, i * RISCV_REGISTER_SIZE);
@@ -251,7 +251,7 @@ static void emit_be_MemPerm(ir_node const *const node)
if (omit_fp) {
offset += (memperm_arity * RISCV_REGISTER_SIZE);
}
- arch_register_t const *const reg = arch_register_for_index(&riscv_reg_classes[CLASS_riscv_gp], i + 9);
+ arch_register_t const *const reg = arch_register_for_index(&riscv_reg_classes[CLASS_riscv_gp], i + 13);
riscv_emitf(node, "sw\t%s, %d(%s)", reg->name, offset, frame_base);
/* restore register */
riscv_emitf(node, "lw\t%s, %d(sp)", reg->name, i * RISCV_REGISTER_SIZE);