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authorMaximilian Stemmer-Grabow <mail@mxsg.de>2021-09-09 14:53:53 +0200
committerAndreas Fried <andreas.fried@kit.edu>2021-12-02 12:57:28 +0100
commit351e546d13441a703e820d81b2ec2cdc2a67c8af (patch)
treeaa91a52260cb77691baa98fef7854fe4690d1c21
parent04ea33223bbd1a30216fdf738326060ca3003a95 (diff)
Add RISC-V configuration for rv32imac arch
-rw-r--r--ir/be/riscv/riscv_bearch.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/ir/be/riscv/riscv_bearch.c b/ir/be/riscv/riscv_bearch.c
index f0a57fb..47947c7 100644
--- a/ir/be/riscv/riscv_bearch.c
+++ b/ir/be/riscv/riscv_bearch.c
@@ -59,11 +59,13 @@ static lc_opt_enum_int_var_t abi_var = {
typedef enum {
rv32imafd,
rv32ima,
+ rv32imac,
} riscv_isa_t;
static const lc_opt_enum_int_items_t isa_items[] = {
{ "rv32g", rv32imafd },
{ "rv32imafd", rv32imafd },
{ "rv32ima", rv32ima },
+ { "rv32imac", rv32imac },
{ NULL, 0 },
};
@@ -134,7 +136,7 @@ static void riscv_init(void)
ir_target.float_int_overflow = ir_overflow_min_max;
ir_platform_set_va_list_type_pointer();
- use_softfloat = ((riscv_isa_t)isa == rv32ima);
+ use_softfloat = ((riscv_isa_t)isa == rv32ima || (riscv_isa_t)isa == rv32imac);
if (use_softfloat && (riscv_abi_t)abi == ilp32d) {
panic("requested ABI requires -march to subsume the 'D' extension");
} else if (!use_softfloat && (riscv_abi_t)abi == ilp32) {