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authorAndreas Fried <andreas.fried@kit.edu>2021-08-03 11:47:33 +0200
committerAndreas Fried <andreas.fried@kit.edu>2021-12-02 12:57:28 +0100
commit04ea33223bbd1a30216fdf738326060ca3003a95 (patch)
tree929c928fc7855de91cab47dcb874ca3cdc7b84b0
parent7a562aca51c910b11cc7d29d5863bae3a7e79829 (diff)
riscv: Call ir_lower_mode_b during target lowering.
Fixes backend/amd64_modeb.c, opt/ifconv7.c.
-rw-r--r--ir/be/riscv/riscv_bearch.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/ir/be/riscv/riscv_bearch.c b/ir/be/riscv/riscv_bearch.c
index 138951e..f0a57fb 100644
--- a/ir/be/riscv/riscv_bearch.c
+++ b/ir/be/riscv/riscv_bearch.c
@@ -29,6 +29,7 @@
#include "lower_alloc.h"
#include "lower_builtins.h"
#include "lower_calls.h"
+#include "lower_mode_b.h"
#include "lower_softfloat.h"
#include "lowering.h"
#include "platform_t.h"
@@ -558,6 +559,8 @@ static void riscv_lower_for_target(void)
be_after_irp_transform("lower-64");
foreach_irp_irg(i, irg) {
+ ir_lower_mode_b(irg, mode_gp);
+ be_after_transform(irg, "lower-modeb");
lower_alloc(irg, RISCV_PO2_STACK_ALIGNMENT);
be_after_transform(irg, "lower-alloc");
}