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authorJohannes Bucher <johannes.bucher2@student.kit.edu>2019-05-17 16:59:58 +0200
committerJohannes Bucher <johannes.bucher2@student.kit.edu>2019-05-17 16:59:58 +0200
commitba3a2e484b321d284bbc5fbc41bd58505e12cf72 (patch)
tree4a85a7c5bb713d93d68abcc31138908c867fa933
parent5d8d3b233eb47bf1c317c7c822983d5524535653 (diff)
riscv: support extension from mode Hu (16 bit) to machine size
-rw-r--r--ir/be/riscv/riscv_transform.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/ir/be/riscv/riscv_transform.c b/ir/be/riscv/riscv_transform.c
index f2c2f18..8f30c9c 100644
--- a/ir/be/riscv/riscv_transform.c
+++ b/ir/be/riscv/riscv_transform.c
@@ -132,8 +132,12 @@ static ir_node *make_extension(dbg_info *const dbgi, ir_node *const op, unsigned
return sra;
} else if (op_size == 8) {
return new_bd_riscv_andi(dbgi, block, new_op, NULL, (1U << op_size) - 1);
+ } else {
+ int32_t const val = RISCV_MACHINE_SIZE - op_size;
+ ir_node *const sll = new_bd_riscv_slli(dbgi, block, new_op, NULL, val);
+ ir_node *const srl = new_bd_riscv_srli(dbgi, block, sll, NULL, val);
+ return srl;
}
- TODO(op);
}
static ir_node *extend_value(ir_node *const val)