11 #include "gen_sparc_regalloc_if.h"
12 #include "bearch_sparc_t.h"
14 const arch_register_req_t sparc_class_reg_req_flags = {
15 .cls = &sparc_reg_classes[CLASS_sparc_flags],
18 static const unsigned sparc_limited_flags_psr[] = { (1U << REG_FLAGS_PSR) };
19 const arch_register_req_t sparc_single_reg_req_flags_psr = {
20 .cls = &sparc_reg_classes[CLASS_sparc_flags],
21 .limited = sparc_limited_flags_psr,
24 const arch_register_req_t sparc_class_reg_req_fp = {
25 .cls = &sparc_reg_classes[CLASS_sparc_fp],
28 static const unsigned sparc_limited_fp_f0[] = { (1U << REG_FP_F0), 0 };
29 const arch_register_req_t sparc_single_reg_req_fp_f0 = {
30 .cls = &sparc_reg_classes[CLASS_sparc_fp],
31 .limited = sparc_limited_fp_f0,
34 static const unsigned sparc_limited_fp_f1[] = { (1U << REG_FP_F1), 0 };
35 const arch_register_req_t sparc_single_reg_req_fp_f1 = {
36 .cls = &sparc_reg_classes[CLASS_sparc_fp],
37 .limited = sparc_limited_fp_f1,
40 static const unsigned sparc_limited_fp_f2[] = { (1U << REG_FP_F2), 0 };
41 const arch_register_req_t sparc_single_reg_req_fp_f2 = {
42 .cls = &sparc_reg_classes[CLASS_sparc_fp],
43 .limited = sparc_limited_fp_f2,
46 static const unsigned sparc_limited_fp_f3[] = { (1U << REG_FP_F3), 0 };
47 const arch_register_req_t sparc_single_reg_req_fp_f3 = {
48 .cls = &sparc_reg_classes[CLASS_sparc_fp],
49 .limited = sparc_limited_fp_f3,
52 static const unsigned sparc_limited_fp_f4[] = { (1U << REG_FP_F4), 0 };
53 const arch_register_req_t sparc_single_reg_req_fp_f4 = {
54 .cls = &sparc_reg_classes[CLASS_sparc_fp],
55 .limited = sparc_limited_fp_f4,
58 static const unsigned sparc_limited_fp_f5[] = { (1U << REG_FP_F5), 0 };
59 const arch_register_req_t sparc_single_reg_req_fp_f5 = {
60 .cls = &sparc_reg_classes[CLASS_sparc_fp],
61 .limited = sparc_limited_fp_f5,
64 static const unsigned sparc_limited_fp_f6[] = { (1U << REG_FP_F6), 0 };
65 const arch_register_req_t sparc_single_reg_req_fp_f6 = {
66 .cls = &sparc_reg_classes[CLASS_sparc_fp],
67 .limited = sparc_limited_fp_f6,
70 static const unsigned sparc_limited_fp_f7[] = { (1U << REG_FP_F7), 0 };
71 const arch_register_req_t sparc_single_reg_req_fp_f7 = {
72 .cls = &sparc_reg_classes[CLASS_sparc_fp],
73 .limited = sparc_limited_fp_f7,
76 static const unsigned sparc_limited_fp_f8[] = { (1U << REG_FP_F8), 0 };
77 const arch_register_req_t sparc_single_reg_req_fp_f8 = {
78 .cls = &sparc_reg_classes[CLASS_sparc_fp],
79 .limited = sparc_limited_fp_f8,
82 static const unsigned sparc_limited_fp_f9[] = { (1U << REG_FP_F9), 0 };
83 const arch_register_req_t sparc_single_reg_req_fp_f9 = {
84 .cls = &sparc_reg_classes[CLASS_sparc_fp],
85 .limited = sparc_limited_fp_f9,
88 static const unsigned sparc_limited_fp_f10[] = { (1U << REG_FP_F10), 0 };
89 const arch_register_req_t sparc_single_reg_req_fp_f10 = {
90 .cls = &sparc_reg_classes[CLASS_sparc_fp],
91 .limited = sparc_limited_fp_f10,
94 static const unsigned sparc_limited_fp_f11[] = { (1U << REG_FP_F11), 0 };
95 const arch_register_req_t sparc_single_reg_req_fp_f11 = {
96 .cls = &sparc_reg_classes[CLASS_sparc_fp],
97 .limited = sparc_limited_fp_f11,
100 static const unsigned sparc_limited_fp_f12[] = { (1U << REG_FP_F12), 0 };
101 const arch_register_req_t sparc_single_reg_req_fp_f12 = {
102 .cls = &sparc_reg_classes[CLASS_sparc_fp],
103 .limited = sparc_limited_fp_f12,
106 static const unsigned sparc_limited_fp_f13[] = { (1U << REG_FP_F13), 0 };
107 const arch_register_req_t sparc_single_reg_req_fp_f13 = {
108 .cls = &sparc_reg_classes[CLASS_sparc_fp],
109 .limited = sparc_limited_fp_f13,
112 static const unsigned sparc_limited_fp_f14[] = { (1U << REG_FP_F14), 0 };
113 const arch_register_req_t sparc_single_reg_req_fp_f14 = {
114 .cls = &sparc_reg_classes[CLASS_sparc_fp],
115 .limited = sparc_limited_fp_f14,
118 static const unsigned sparc_limited_fp_f15[] = { (1U << REG_FP_F15), 0 };
119 const arch_register_req_t sparc_single_reg_req_fp_f15 = {
120 .cls = &sparc_reg_classes[CLASS_sparc_fp],
121 .limited = sparc_limited_fp_f15,
124 static const unsigned sparc_limited_fp_f16[] = { (1U << REG_FP_F16), 0 };
125 const arch_register_req_t sparc_single_reg_req_fp_f16 = {
126 .cls = &sparc_reg_classes[CLASS_sparc_fp],
127 .limited = sparc_limited_fp_f16,
130 static const unsigned sparc_limited_fp_f17[] = { (1U << REG_FP_F17), 0 };
131 const arch_register_req_t sparc_single_reg_req_fp_f17 = {
132 .cls = &sparc_reg_classes[CLASS_sparc_fp],
133 .limited = sparc_limited_fp_f17,
136 static const unsigned sparc_limited_fp_f18[] = { (1U << REG_FP_F18), 0 };
137 const arch_register_req_t sparc_single_reg_req_fp_f18 = {
138 .cls = &sparc_reg_classes[CLASS_sparc_fp],
139 .limited = sparc_limited_fp_f18,
142 static const unsigned sparc_limited_fp_f19[] = { (1U << REG_FP_F19), 0 };
143 const arch_register_req_t sparc_single_reg_req_fp_f19 = {
144 .cls = &sparc_reg_classes[CLASS_sparc_fp],
145 .limited = sparc_limited_fp_f19,
148 static const unsigned sparc_limited_fp_f20[] = { (1U << REG_FP_F20), 0 };
149 const arch_register_req_t sparc_single_reg_req_fp_f20 = {
150 .cls = &sparc_reg_classes[CLASS_sparc_fp],
151 .limited = sparc_limited_fp_f20,
154 static const unsigned sparc_limited_fp_f21[] = { (1U << REG_FP_F21), 0 };
155 const arch_register_req_t sparc_single_reg_req_fp_f21 = {
156 .cls = &sparc_reg_classes[CLASS_sparc_fp],
157 .limited = sparc_limited_fp_f21,
160 static const unsigned sparc_limited_fp_f22[] = { (1U << REG_FP_F22), 0 };
161 const arch_register_req_t sparc_single_reg_req_fp_f22 = {
162 .cls = &sparc_reg_classes[CLASS_sparc_fp],
163 .limited = sparc_limited_fp_f22,
166 static const unsigned sparc_limited_fp_f23[] = { (1U << REG_FP_F23), 0 };
167 const arch_register_req_t sparc_single_reg_req_fp_f23 = {
168 .cls = &sparc_reg_classes[CLASS_sparc_fp],
169 .limited = sparc_limited_fp_f23,
172 static const unsigned sparc_limited_fp_f24[] = { (1U << REG_FP_F24), 0 };
173 const arch_register_req_t sparc_single_reg_req_fp_f24 = {
174 .cls = &sparc_reg_classes[CLASS_sparc_fp],
175 .limited = sparc_limited_fp_f24,
178 static const unsigned sparc_limited_fp_f25[] = { (1U << REG_FP_F25), 0 };
179 const arch_register_req_t sparc_single_reg_req_fp_f25 = {
180 .cls = &sparc_reg_classes[CLASS_sparc_fp],
181 .limited = sparc_limited_fp_f25,
184 static const unsigned sparc_limited_fp_f26[] = { (1U << REG_FP_F26), 0 };
185 const arch_register_req_t sparc_single_reg_req_fp_f26 = {
186 .cls = &sparc_reg_classes[CLASS_sparc_fp],
187 .limited = sparc_limited_fp_f26,
190 static const unsigned sparc_limited_fp_f27[] = { (1U << REG_FP_F27), 0 };
191 const arch_register_req_t sparc_single_reg_req_fp_f27 = {
192 .cls = &sparc_reg_classes[CLASS_sparc_fp],
193 .limited = sparc_limited_fp_f27,
196 static const unsigned sparc_limited_fp_f28[] = { (1U << REG_FP_F28), 0 };
197 const arch_register_req_t sparc_single_reg_req_fp_f28 = {
198 .cls = &sparc_reg_classes[CLASS_sparc_fp],
199 .limited = sparc_limited_fp_f28,
202 static const unsigned sparc_limited_fp_f29[] = { (1U << REG_FP_F29), 0 };
203 const arch_register_req_t sparc_single_reg_req_fp_f29 = {
204 .cls = &sparc_reg_classes[CLASS_sparc_fp],
205 .limited = sparc_limited_fp_f29,
208 static const unsigned sparc_limited_fp_f30[] = { (1U << REG_FP_F30), 0 };
209 const arch_register_req_t sparc_single_reg_req_fp_f30 = {
210 .cls = &sparc_reg_classes[CLASS_sparc_fp],
211 .limited = sparc_limited_fp_f30,
214 static const unsigned sparc_limited_fp_f31[] = { (1U << REG_FP_F31), 0 };
215 const arch_register_req_t sparc_single_reg_req_fp_f31 = {
216 .cls = &sparc_reg_classes[CLASS_sparc_fp],
217 .limited = sparc_limited_fp_f31,
220 const arch_register_req_t sparc_class_reg_req_fpflags = {
221 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
224 static const unsigned sparc_limited_fpflags_fsr[] = { (1U << REG_FPFLAGS_FSR) };
225 const arch_register_req_t sparc_single_reg_req_fpflags_fsr = {
226 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
227 .limited = sparc_limited_fpflags_fsr,
230 const arch_register_req_t sparc_class_reg_req_gp = {
231 .cls = &sparc_reg_classes[CLASS_sparc_gp],
234 static const unsigned sparc_limited_gp_l0[] = { (1U << REG_GP_L0), 0 };
235 const arch_register_req_t sparc_single_reg_req_gp_l0 = {
236 .cls = &sparc_reg_classes[CLASS_sparc_gp],
237 .limited = sparc_limited_gp_l0,
240 static const unsigned sparc_limited_gp_l1[] = { (1U << REG_GP_L1), 0 };
241 const arch_register_req_t sparc_single_reg_req_gp_l1 = {
242 .cls = &sparc_reg_classes[CLASS_sparc_gp],
243 .limited = sparc_limited_gp_l1,
246 static const unsigned sparc_limited_gp_l2[] = { (1U << REG_GP_L2), 0 };
247 const arch_register_req_t sparc_single_reg_req_gp_l2 = {
248 .cls = &sparc_reg_classes[CLASS_sparc_gp],
249 .limited = sparc_limited_gp_l2,
252 static const unsigned sparc_limited_gp_l3[] = { (1U << REG_GP_L3), 0 };
253 const arch_register_req_t sparc_single_reg_req_gp_l3 = {
254 .cls = &sparc_reg_classes[CLASS_sparc_gp],
255 .limited = sparc_limited_gp_l3,
258 static const unsigned sparc_limited_gp_l4[] = { (1U << REG_GP_L4), 0 };
259 const arch_register_req_t sparc_single_reg_req_gp_l4 = {
260 .cls = &sparc_reg_classes[CLASS_sparc_gp],
261 .limited = sparc_limited_gp_l4,
264 static const unsigned sparc_limited_gp_l5[] = { (1U << REG_GP_L5), 0 };
265 const arch_register_req_t sparc_single_reg_req_gp_l5 = {
266 .cls = &sparc_reg_classes[CLASS_sparc_gp],
267 .limited = sparc_limited_gp_l5,
270 static const unsigned sparc_limited_gp_l6[] = { (1U << REG_GP_L6), 0 };
271 const arch_register_req_t sparc_single_reg_req_gp_l6 = {
272 .cls = &sparc_reg_classes[CLASS_sparc_gp],
273 .limited = sparc_limited_gp_l6,
276 static const unsigned sparc_limited_gp_l7[] = { (1U << REG_GP_L7), 0 };
277 const arch_register_req_t sparc_single_reg_req_gp_l7 = {
278 .cls = &sparc_reg_classes[CLASS_sparc_gp],
279 .limited = sparc_limited_gp_l7,
282 static const unsigned sparc_limited_gp_g0[] = { (1U << REG_GP_G0), 0 };
283 const arch_register_req_t sparc_single_reg_req_gp_g0 = {
284 .cls = &sparc_reg_classes[CLASS_sparc_gp],
285 .limited = sparc_limited_gp_g0,
288 static const unsigned sparc_limited_gp_g1[] = { (1U << REG_GP_G1), 0 };
289 const arch_register_req_t sparc_single_reg_req_gp_g1 = {
290 .cls = &sparc_reg_classes[CLASS_sparc_gp],
291 .limited = sparc_limited_gp_g1,
294 static const unsigned sparc_limited_gp_g2[] = { (1U << REG_GP_G2), 0 };
295 const arch_register_req_t sparc_single_reg_req_gp_g2 = {
296 .cls = &sparc_reg_classes[CLASS_sparc_gp],
297 .limited = sparc_limited_gp_g2,
300 static const unsigned sparc_limited_gp_g3[] = { (1U << REG_GP_G3), 0 };
301 const arch_register_req_t sparc_single_reg_req_gp_g3 = {
302 .cls = &sparc_reg_classes[CLASS_sparc_gp],
303 .limited = sparc_limited_gp_g3,
306 static const unsigned sparc_limited_gp_g4[] = { (1U << REG_GP_G4), 0 };
307 const arch_register_req_t sparc_single_reg_req_gp_g4 = {
308 .cls = &sparc_reg_classes[CLASS_sparc_gp],
309 .limited = sparc_limited_gp_g4,
312 static const unsigned sparc_limited_gp_g5[] = { (1U << REG_GP_G5), 0 };
313 const arch_register_req_t sparc_single_reg_req_gp_g5 = {
314 .cls = &sparc_reg_classes[CLASS_sparc_gp],
315 .limited = sparc_limited_gp_g5,
318 static const unsigned sparc_limited_gp_g6[] = { (1U << REG_GP_G6), 0 };
319 const arch_register_req_t sparc_single_reg_req_gp_g6 = {
320 .cls = &sparc_reg_classes[CLASS_sparc_gp],
321 .limited = sparc_limited_gp_g6,
324 static const unsigned sparc_limited_gp_g7[] = { (1U << REG_GP_G7), 0 };
325 const arch_register_req_t sparc_single_reg_req_gp_g7 = {
326 .cls = &sparc_reg_classes[CLASS_sparc_gp],
327 .limited = sparc_limited_gp_g7,
330 static const unsigned sparc_limited_gp_o0[] = { (1U << REG_GP_O0), 0 };
331 const arch_register_req_t sparc_single_reg_req_gp_o0 = {
332 .cls = &sparc_reg_classes[CLASS_sparc_gp],
333 .limited = sparc_limited_gp_o0,
336 static const unsigned sparc_limited_gp_o1[] = { (1U << REG_GP_O1), 0 };
337 const arch_register_req_t sparc_single_reg_req_gp_o1 = {
338 .cls = &sparc_reg_classes[CLASS_sparc_gp],
339 .limited = sparc_limited_gp_o1,
342 static const unsigned sparc_limited_gp_o2[] = { (1U << REG_GP_O2), 0 };
343 const arch_register_req_t sparc_single_reg_req_gp_o2 = {
344 .cls = &sparc_reg_classes[CLASS_sparc_gp],
345 .limited = sparc_limited_gp_o2,
348 static const unsigned sparc_limited_gp_o3[] = { (1U << REG_GP_O3), 0 };
349 const arch_register_req_t sparc_single_reg_req_gp_o3 = {
350 .cls = &sparc_reg_classes[CLASS_sparc_gp],
351 .limited = sparc_limited_gp_o3,
354 static const unsigned sparc_limited_gp_o4[] = { (1U << REG_GP_O4), 0 };
355 const arch_register_req_t sparc_single_reg_req_gp_o4 = {
356 .cls = &sparc_reg_classes[CLASS_sparc_gp],
357 .limited = sparc_limited_gp_o4,
360 static const unsigned sparc_limited_gp_o5[] = { (1U << REG_GP_O5), 0 };
361 const arch_register_req_t sparc_single_reg_req_gp_o5 = {
362 .cls = &sparc_reg_classes[CLASS_sparc_gp],
363 .limited = sparc_limited_gp_o5,
366 static const unsigned sparc_limited_gp_sp[] = { (1U << REG_GP_SP), 0 };
367 const arch_register_req_t sparc_single_reg_req_gp_sp = {
368 .cls = &sparc_reg_classes[CLASS_sparc_gp],
369 .limited = sparc_limited_gp_sp,
372 static const unsigned sparc_limited_gp_o7[] = { (1U << REG_GP_O7), 0 };
373 const arch_register_req_t sparc_single_reg_req_gp_o7 = {
374 .cls = &sparc_reg_classes[CLASS_sparc_gp],
375 .limited = sparc_limited_gp_o7,
378 static const unsigned sparc_limited_gp_i0[] = { (1U << REG_GP_I0), 0 };
379 const arch_register_req_t sparc_single_reg_req_gp_i0 = {
380 .cls = &sparc_reg_classes[CLASS_sparc_gp],
381 .limited = sparc_limited_gp_i0,
384 static const unsigned sparc_limited_gp_i1[] = { (1U << REG_GP_I1), 0 };
385 const arch_register_req_t sparc_single_reg_req_gp_i1 = {
386 .cls = &sparc_reg_classes[CLASS_sparc_gp],
387 .limited = sparc_limited_gp_i1,
390 static const unsigned sparc_limited_gp_i2[] = { (1U << REG_GP_I2), 0 };
391 const arch_register_req_t sparc_single_reg_req_gp_i2 = {
392 .cls = &sparc_reg_classes[CLASS_sparc_gp],
393 .limited = sparc_limited_gp_i2,
396 static const unsigned sparc_limited_gp_i3[] = { (1U << REG_GP_I3), 0 };
397 const arch_register_req_t sparc_single_reg_req_gp_i3 = {
398 .cls = &sparc_reg_classes[CLASS_sparc_gp],
399 .limited = sparc_limited_gp_i3,
402 static const unsigned sparc_limited_gp_i4[] = { (1U << REG_GP_I4), 0 };
403 const arch_register_req_t sparc_single_reg_req_gp_i4 = {
404 .cls = &sparc_reg_classes[CLASS_sparc_gp],
405 .limited = sparc_limited_gp_i4,
408 static const unsigned sparc_limited_gp_i5[] = { (1U << REG_GP_I5), 0 };
409 const arch_register_req_t sparc_single_reg_req_gp_i5 = {
410 .cls = &sparc_reg_classes[CLASS_sparc_gp],
411 .limited = sparc_limited_gp_i5,
414 static const unsigned sparc_limited_gp_fp[] = { (1U << REG_GP_FP), 0 };
415 const arch_register_req_t sparc_single_reg_req_gp_fp = {
416 .cls = &sparc_reg_classes[CLASS_sparc_gp],
417 .limited = sparc_limited_gp_fp,
420 static const unsigned sparc_limited_gp_i7[] = { (1U << REG_GP_I7), 0 };
421 const arch_register_req_t sparc_single_reg_req_gp_i7 = {
422 .cls = &sparc_reg_classes[CLASS_sparc_gp],
423 .limited = sparc_limited_gp_i7,
426 const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
427 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
430 static const unsigned sparc_limited_mul_div_high_res_y[] = { (1U << REG_MUL_DIV_HIGH_RES_Y) };
431 const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
432 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
433 .limited = sparc_limited_mul_div_high_res_y,
438 arch_register_class_t sparc_reg_classes[] = {
440 .name =
"sparc_flags",
442 .regs = &sparc_registers[REG_PSR],
443 .class_req = &sparc_class_reg_req_flags,
444 .index = CLASS_sparc_flags,
451 .regs = &sparc_registers[REG_F0],
452 .class_req = &sparc_class_reg_req_fp,
453 .index = CLASS_sparc_fp,
458 .name =
"sparc_fpflags",
460 .regs = &sparc_registers[REG_FSR],
461 .class_req = &sparc_class_reg_req_fpflags,
462 .index = CLASS_sparc_fpflags,
469 .regs = &sparc_registers[REG_L0],
470 .class_req = &sparc_class_reg_req_gp,
471 .index = CLASS_sparc_gp,
476 .name =
"sparc_mul_div_high_res",
478 .regs = &sparc_registers[REG_Y],
479 .class_req = &sparc_class_reg_req_mul_div_high_res,
480 .index = CLASS_sparc_mul_div_high_res,
488 const arch_register_t sparc_registers[] = {
491 .cls = &sparc_reg_classes[CLASS_sparc_flags],
492 .single_req = &sparc_single_reg_req_flags_psr,
493 .index = REG_FLAGS_PSR,
494 .global_index = REG_PSR,
496 .encoding = REG_FLAGS_PSR,
501 .cls = &sparc_reg_classes[CLASS_sparc_fp],
502 .single_req = &sparc_single_reg_req_fp_f0,
504 .global_index = REG_F0,
511 .cls = &sparc_reg_classes[CLASS_sparc_fp],
512 .single_req = &sparc_single_reg_req_fp_f1,
514 .global_index = REG_F1,
521 .cls = &sparc_reg_classes[CLASS_sparc_fp],
522 .single_req = &sparc_single_reg_req_fp_f2,
524 .global_index = REG_F2,
531 .cls = &sparc_reg_classes[CLASS_sparc_fp],
532 .single_req = &sparc_single_reg_req_fp_f3,
534 .global_index = REG_F3,
541 .cls = &sparc_reg_classes[CLASS_sparc_fp],
542 .single_req = &sparc_single_reg_req_fp_f4,
544 .global_index = REG_F4,
551 .cls = &sparc_reg_classes[CLASS_sparc_fp],
552 .single_req = &sparc_single_reg_req_fp_f5,
554 .global_index = REG_F5,
561 .cls = &sparc_reg_classes[CLASS_sparc_fp],
562 .single_req = &sparc_single_reg_req_fp_f6,
564 .global_index = REG_F6,
571 .cls = &sparc_reg_classes[CLASS_sparc_fp],
572 .single_req = &sparc_single_reg_req_fp_f7,
574 .global_index = REG_F7,
581 .cls = &sparc_reg_classes[CLASS_sparc_fp],
582 .single_req = &sparc_single_reg_req_fp_f8,
584 .global_index = REG_F8,
591 .cls = &sparc_reg_classes[CLASS_sparc_fp],
592 .single_req = &sparc_single_reg_req_fp_f9,
594 .global_index = REG_F9,
601 .cls = &sparc_reg_classes[CLASS_sparc_fp],
602 .single_req = &sparc_single_reg_req_fp_f10,
604 .global_index = REG_F10,
611 .cls = &sparc_reg_classes[CLASS_sparc_fp],
612 .single_req = &sparc_single_reg_req_fp_f11,
614 .global_index = REG_F11,
621 .cls = &sparc_reg_classes[CLASS_sparc_fp],
622 .single_req = &sparc_single_reg_req_fp_f12,
624 .global_index = REG_F12,
631 .cls = &sparc_reg_classes[CLASS_sparc_fp],
632 .single_req = &sparc_single_reg_req_fp_f13,
634 .global_index = REG_F13,
641 .cls = &sparc_reg_classes[CLASS_sparc_fp],
642 .single_req = &sparc_single_reg_req_fp_f14,
644 .global_index = REG_F14,
651 .cls = &sparc_reg_classes[CLASS_sparc_fp],
652 .single_req = &sparc_single_reg_req_fp_f15,
654 .global_index = REG_F15,
661 .cls = &sparc_reg_classes[CLASS_sparc_fp],
662 .single_req = &sparc_single_reg_req_fp_f16,
664 .global_index = REG_F16,
671 .cls = &sparc_reg_classes[CLASS_sparc_fp],
672 .single_req = &sparc_single_reg_req_fp_f17,
674 .global_index = REG_F17,
681 .cls = &sparc_reg_classes[CLASS_sparc_fp],
682 .single_req = &sparc_single_reg_req_fp_f18,
684 .global_index = REG_F18,
691 .cls = &sparc_reg_classes[CLASS_sparc_fp],
692 .single_req = &sparc_single_reg_req_fp_f19,
694 .global_index = REG_F19,
701 .cls = &sparc_reg_classes[CLASS_sparc_fp],
702 .single_req = &sparc_single_reg_req_fp_f20,
704 .global_index = REG_F20,
711 .cls = &sparc_reg_classes[CLASS_sparc_fp],
712 .single_req = &sparc_single_reg_req_fp_f21,
714 .global_index = REG_F21,
721 .cls = &sparc_reg_classes[CLASS_sparc_fp],
722 .single_req = &sparc_single_reg_req_fp_f22,
724 .global_index = REG_F22,
731 .cls = &sparc_reg_classes[CLASS_sparc_fp],
732 .single_req = &sparc_single_reg_req_fp_f23,
734 .global_index = REG_F23,
741 .cls = &sparc_reg_classes[CLASS_sparc_fp],
742 .single_req = &sparc_single_reg_req_fp_f24,
744 .global_index = REG_F24,
751 .cls = &sparc_reg_classes[CLASS_sparc_fp],
752 .single_req = &sparc_single_reg_req_fp_f25,
754 .global_index = REG_F25,
761 .cls = &sparc_reg_classes[CLASS_sparc_fp],
762 .single_req = &sparc_single_reg_req_fp_f26,
764 .global_index = REG_F26,
771 .cls = &sparc_reg_classes[CLASS_sparc_fp],
772 .single_req = &sparc_single_reg_req_fp_f27,
774 .global_index = REG_F27,
781 .cls = &sparc_reg_classes[CLASS_sparc_fp],
782 .single_req = &sparc_single_reg_req_fp_f28,
784 .global_index = REG_F28,
791 .cls = &sparc_reg_classes[CLASS_sparc_fp],
792 .single_req = &sparc_single_reg_req_fp_f29,
794 .global_index = REG_F29,
801 .cls = &sparc_reg_classes[CLASS_sparc_fp],
802 .single_req = &sparc_single_reg_req_fp_f30,
804 .global_index = REG_F30,
811 .cls = &sparc_reg_classes[CLASS_sparc_fp],
812 .single_req = &sparc_single_reg_req_fp_f31,
814 .global_index = REG_F31,
821 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
822 .single_req = &sparc_single_reg_req_fpflags_fsr,
823 .index = REG_FPFLAGS_FSR,
824 .global_index = REG_FSR,
826 .encoding = REG_FPFLAGS_FSR,
831 .cls = &sparc_reg_classes[CLASS_sparc_gp],
832 .single_req = &sparc_single_reg_req_gp_l0,
834 .global_index = REG_L0,
841 .cls = &sparc_reg_classes[CLASS_sparc_gp],
842 .single_req = &sparc_single_reg_req_gp_l1,
844 .global_index = REG_L1,
851 .cls = &sparc_reg_classes[CLASS_sparc_gp],
852 .single_req = &sparc_single_reg_req_gp_l2,
854 .global_index = REG_L2,
861 .cls = &sparc_reg_classes[CLASS_sparc_gp],
862 .single_req = &sparc_single_reg_req_gp_l3,
864 .global_index = REG_L3,
871 .cls = &sparc_reg_classes[CLASS_sparc_gp],
872 .single_req = &sparc_single_reg_req_gp_l4,
874 .global_index = REG_L4,
881 .cls = &sparc_reg_classes[CLASS_sparc_gp],
882 .single_req = &sparc_single_reg_req_gp_l5,
884 .global_index = REG_L5,
891 .cls = &sparc_reg_classes[CLASS_sparc_gp],
892 .single_req = &sparc_single_reg_req_gp_l6,
894 .global_index = REG_L6,
901 .cls = &sparc_reg_classes[CLASS_sparc_gp],
902 .single_req = &sparc_single_reg_req_gp_l7,
904 .global_index = REG_L7,
911 .cls = &sparc_reg_classes[CLASS_sparc_gp],
912 .single_req = &sparc_single_reg_req_gp_g0,
914 .global_index = REG_G0,
921 .cls = &sparc_reg_classes[CLASS_sparc_gp],
922 .single_req = &sparc_single_reg_req_gp_g1,
924 .global_index = REG_G1,
931 .cls = &sparc_reg_classes[CLASS_sparc_gp],
932 .single_req = &sparc_single_reg_req_gp_g2,
934 .global_index = REG_G2,
941 .cls = &sparc_reg_classes[CLASS_sparc_gp],
942 .single_req = &sparc_single_reg_req_gp_g3,
944 .global_index = REG_G3,
951 .cls = &sparc_reg_classes[CLASS_sparc_gp],
952 .single_req = &sparc_single_reg_req_gp_g4,
954 .global_index = REG_G4,
961 .cls = &sparc_reg_classes[CLASS_sparc_gp],
962 .single_req = &sparc_single_reg_req_gp_g5,
964 .global_index = REG_G5,
971 .cls = &sparc_reg_classes[CLASS_sparc_gp],
972 .single_req = &sparc_single_reg_req_gp_g6,
974 .global_index = REG_G6,
981 .cls = &sparc_reg_classes[CLASS_sparc_gp],
982 .single_req = &sparc_single_reg_req_gp_g7,
984 .global_index = REG_G7,
991 .cls = &sparc_reg_classes[CLASS_sparc_gp],
992 .single_req = &sparc_single_reg_req_gp_o0,
994 .global_index = REG_O0,
1001 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1002 .single_req = &sparc_single_reg_req_gp_o1,
1004 .global_index = REG_O1,
1007 .is_virtual =
false,
1011 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1012 .single_req = &sparc_single_reg_req_gp_o2,
1014 .global_index = REG_O2,
1017 .is_virtual =
false,
1021 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1022 .single_req = &sparc_single_reg_req_gp_o3,
1024 .global_index = REG_O3,
1027 .is_virtual =
false,
1031 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1032 .single_req = &sparc_single_reg_req_gp_o4,
1034 .global_index = REG_O4,
1037 .is_virtual =
false,
1041 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1042 .single_req = &sparc_single_reg_req_gp_o5,
1044 .global_index = REG_O5,
1047 .is_virtual =
false,
1051 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1052 .single_req = &sparc_single_reg_req_gp_sp,
1054 .global_index = REG_SP,
1057 .is_virtual =
false,
1061 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1062 .single_req = &sparc_single_reg_req_gp_o7,
1064 .global_index = REG_O7,
1067 .is_virtual =
false,
1071 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1072 .single_req = &sparc_single_reg_req_gp_i0,
1074 .global_index = REG_I0,
1077 .is_virtual =
false,
1081 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1082 .single_req = &sparc_single_reg_req_gp_i1,
1084 .global_index = REG_I1,
1087 .is_virtual =
false,
1091 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1092 .single_req = &sparc_single_reg_req_gp_i2,
1094 .global_index = REG_I2,
1097 .is_virtual =
false,
1101 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1102 .single_req = &sparc_single_reg_req_gp_i3,
1104 .global_index = REG_I3,
1107 .is_virtual =
false,
1111 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1112 .single_req = &sparc_single_reg_req_gp_i4,
1114 .global_index = REG_I4,
1117 .is_virtual =
false,
1121 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1122 .single_req = &sparc_single_reg_req_gp_i5,
1124 .global_index = REG_I5,
1127 .is_virtual =
false,
1131 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1132 .single_req = &sparc_single_reg_req_gp_fp,
1134 .global_index = REG_FP,
1137 .is_virtual =
false,
1141 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1142 .single_req = &sparc_single_reg_req_gp_i7,
1144 .global_index = REG_I7,
1147 .is_virtual =
false,
1151 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1152 .single_req = &sparc_single_reg_req_mul_div_high_res_y,
1153 .index = REG_MUL_DIV_HIGH_RES_Y,
1154 .global_index = REG_Y,
1156 .encoding = REG_MUL_DIV_HIGH_RES_Y,
1157 .is_virtual =
false,
1165 void sparc_register_init(
void)
1167 sparc_reg_classes[CLASS_sparc_flags].mode =
mode_Bu;
1168 sparc_reg_classes[CLASS_sparc_fp].mode =
mode_F;
1169 sparc_reg_classes[CLASS_sparc_fpflags].mode =
mode_Bu;
1170 sparc_reg_classes[CLASS_sparc_gp].mode =
mode_Iu;
1171 sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode =
mode_Iu;
ir_mode * mode_F
ieee754 binary32 float (single precision)