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gen_sparc_regalloc_if.c
1 
11 #include "gen_sparc_regalloc_if.h"
12 #include "bearch_sparc_t.h"
13 
14 const arch_register_req_t sparc_class_reg_req_flags = {
15  .cls = &sparc_reg_classes[CLASS_sparc_flags],
16  .width = 1,
17 };
18 static const unsigned sparc_limited_flags_psr[] = { (1U << REG_FLAGS_PSR) };
19 const arch_register_req_t sparc_single_reg_req_flags_psr = {
20  .cls = &sparc_reg_classes[CLASS_sparc_flags],
21  .limited = sparc_limited_flags_psr,
22  .width = 1,
23 };
24 const arch_register_req_t sparc_class_reg_req_fp = {
25  .cls = &sparc_reg_classes[CLASS_sparc_fp],
26  .width = 1,
27 };
28 static const unsigned sparc_limited_fp_f0[] = { (1U << REG_FP_F0), 0 };
29 const arch_register_req_t sparc_single_reg_req_fp_f0 = {
30  .cls = &sparc_reg_classes[CLASS_sparc_fp],
31  .limited = sparc_limited_fp_f0,
32  .width = 1,
33 };
34 static const unsigned sparc_limited_fp_f1[] = { (1U << REG_FP_F1), 0 };
35 const arch_register_req_t sparc_single_reg_req_fp_f1 = {
36  .cls = &sparc_reg_classes[CLASS_sparc_fp],
37  .limited = sparc_limited_fp_f1,
38  .width = 1,
39 };
40 static const unsigned sparc_limited_fp_f2[] = { (1U << REG_FP_F2), 0 };
41 const arch_register_req_t sparc_single_reg_req_fp_f2 = {
42  .cls = &sparc_reg_classes[CLASS_sparc_fp],
43  .limited = sparc_limited_fp_f2,
44  .width = 1,
45 };
46 static const unsigned sparc_limited_fp_f3[] = { (1U << REG_FP_F3), 0 };
47 const arch_register_req_t sparc_single_reg_req_fp_f3 = {
48  .cls = &sparc_reg_classes[CLASS_sparc_fp],
49  .limited = sparc_limited_fp_f3,
50  .width = 1,
51 };
52 static const unsigned sparc_limited_fp_f4[] = { (1U << REG_FP_F4), 0 };
53 const arch_register_req_t sparc_single_reg_req_fp_f4 = {
54  .cls = &sparc_reg_classes[CLASS_sparc_fp],
55  .limited = sparc_limited_fp_f4,
56  .width = 1,
57 };
58 static const unsigned sparc_limited_fp_f5[] = { (1U << REG_FP_F5), 0 };
59 const arch_register_req_t sparc_single_reg_req_fp_f5 = {
60  .cls = &sparc_reg_classes[CLASS_sparc_fp],
61  .limited = sparc_limited_fp_f5,
62  .width = 1,
63 };
64 static const unsigned sparc_limited_fp_f6[] = { (1U << REG_FP_F6), 0 };
65 const arch_register_req_t sparc_single_reg_req_fp_f6 = {
66  .cls = &sparc_reg_classes[CLASS_sparc_fp],
67  .limited = sparc_limited_fp_f6,
68  .width = 1,
69 };
70 static const unsigned sparc_limited_fp_f7[] = { (1U << REG_FP_F7), 0 };
71 const arch_register_req_t sparc_single_reg_req_fp_f7 = {
72  .cls = &sparc_reg_classes[CLASS_sparc_fp],
73  .limited = sparc_limited_fp_f7,
74  .width = 1,
75 };
76 static const unsigned sparc_limited_fp_f8[] = { (1U << REG_FP_F8), 0 };
77 const arch_register_req_t sparc_single_reg_req_fp_f8 = {
78  .cls = &sparc_reg_classes[CLASS_sparc_fp],
79  .limited = sparc_limited_fp_f8,
80  .width = 1,
81 };
82 static const unsigned sparc_limited_fp_f9[] = { (1U << REG_FP_F9), 0 };
83 const arch_register_req_t sparc_single_reg_req_fp_f9 = {
84  .cls = &sparc_reg_classes[CLASS_sparc_fp],
85  .limited = sparc_limited_fp_f9,
86  .width = 1,
87 };
88 static const unsigned sparc_limited_fp_f10[] = { (1U << REG_FP_F10), 0 };
89 const arch_register_req_t sparc_single_reg_req_fp_f10 = {
90  .cls = &sparc_reg_classes[CLASS_sparc_fp],
91  .limited = sparc_limited_fp_f10,
92  .width = 1,
93 };
94 static const unsigned sparc_limited_fp_f11[] = { (1U << REG_FP_F11), 0 };
95 const arch_register_req_t sparc_single_reg_req_fp_f11 = {
96  .cls = &sparc_reg_classes[CLASS_sparc_fp],
97  .limited = sparc_limited_fp_f11,
98  .width = 1,
99 };
100 static const unsigned sparc_limited_fp_f12[] = { (1U << REG_FP_F12), 0 };
101 const arch_register_req_t sparc_single_reg_req_fp_f12 = {
102  .cls = &sparc_reg_classes[CLASS_sparc_fp],
103  .limited = sparc_limited_fp_f12,
104  .width = 1,
105 };
106 static const unsigned sparc_limited_fp_f13[] = { (1U << REG_FP_F13), 0 };
107 const arch_register_req_t sparc_single_reg_req_fp_f13 = {
108  .cls = &sparc_reg_classes[CLASS_sparc_fp],
109  .limited = sparc_limited_fp_f13,
110  .width = 1,
111 };
112 static const unsigned sparc_limited_fp_f14[] = { (1U << REG_FP_F14), 0 };
113 const arch_register_req_t sparc_single_reg_req_fp_f14 = {
114  .cls = &sparc_reg_classes[CLASS_sparc_fp],
115  .limited = sparc_limited_fp_f14,
116  .width = 1,
117 };
118 static const unsigned sparc_limited_fp_f15[] = { (1U << REG_FP_F15), 0 };
119 const arch_register_req_t sparc_single_reg_req_fp_f15 = {
120  .cls = &sparc_reg_classes[CLASS_sparc_fp],
121  .limited = sparc_limited_fp_f15,
122  .width = 1,
123 };
124 static const unsigned sparc_limited_fp_f16[] = { (1U << REG_FP_F16), 0 };
125 const arch_register_req_t sparc_single_reg_req_fp_f16 = {
126  .cls = &sparc_reg_classes[CLASS_sparc_fp],
127  .limited = sparc_limited_fp_f16,
128  .width = 1,
129 };
130 static const unsigned sparc_limited_fp_f17[] = { (1U << REG_FP_F17), 0 };
131 const arch_register_req_t sparc_single_reg_req_fp_f17 = {
132  .cls = &sparc_reg_classes[CLASS_sparc_fp],
133  .limited = sparc_limited_fp_f17,
134  .width = 1,
135 };
136 static const unsigned sparc_limited_fp_f18[] = { (1U << REG_FP_F18), 0 };
137 const arch_register_req_t sparc_single_reg_req_fp_f18 = {
138  .cls = &sparc_reg_classes[CLASS_sparc_fp],
139  .limited = sparc_limited_fp_f18,
140  .width = 1,
141 };
142 static const unsigned sparc_limited_fp_f19[] = { (1U << REG_FP_F19), 0 };
143 const arch_register_req_t sparc_single_reg_req_fp_f19 = {
144  .cls = &sparc_reg_classes[CLASS_sparc_fp],
145  .limited = sparc_limited_fp_f19,
146  .width = 1,
147 };
148 static const unsigned sparc_limited_fp_f20[] = { (1U << REG_FP_F20), 0 };
149 const arch_register_req_t sparc_single_reg_req_fp_f20 = {
150  .cls = &sparc_reg_classes[CLASS_sparc_fp],
151  .limited = sparc_limited_fp_f20,
152  .width = 1,
153 };
154 static const unsigned sparc_limited_fp_f21[] = { (1U << REG_FP_F21), 0 };
155 const arch_register_req_t sparc_single_reg_req_fp_f21 = {
156  .cls = &sparc_reg_classes[CLASS_sparc_fp],
157  .limited = sparc_limited_fp_f21,
158  .width = 1,
159 };
160 static const unsigned sparc_limited_fp_f22[] = { (1U << REG_FP_F22), 0 };
161 const arch_register_req_t sparc_single_reg_req_fp_f22 = {
162  .cls = &sparc_reg_classes[CLASS_sparc_fp],
163  .limited = sparc_limited_fp_f22,
164  .width = 1,
165 };
166 static const unsigned sparc_limited_fp_f23[] = { (1U << REG_FP_F23), 0 };
167 const arch_register_req_t sparc_single_reg_req_fp_f23 = {
168  .cls = &sparc_reg_classes[CLASS_sparc_fp],
169  .limited = sparc_limited_fp_f23,
170  .width = 1,
171 };
172 static const unsigned sparc_limited_fp_f24[] = { (1U << REG_FP_F24), 0 };
173 const arch_register_req_t sparc_single_reg_req_fp_f24 = {
174  .cls = &sparc_reg_classes[CLASS_sparc_fp],
175  .limited = sparc_limited_fp_f24,
176  .width = 1,
177 };
178 static const unsigned sparc_limited_fp_f25[] = { (1U << REG_FP_F25), 0 };
179 const arch_register_req_t sparc_single_reg_req_fp_f25 = {
180  .cls = &sparc_reg_classes[CLASS_sparc_fp],
181  .limited = sparc_limited_fp_f25,
182  .width = 1,
183 };
184 static const unsigned sparc_limited_fp_f26[] = { (1U << REG_FP_F26), 0 };
185 const arch_register_req_t sparc_single_reg_req_fp_f26 = {
186  .cls = &sparc_reg_classes[CLASS_sparc_fp],
187  .limited = sparc_limited_fp_f26,
188  .width = 1,
189 };
190 static const unsigned sparc_limited_fp_f27[] = { (1U << REG_FP_F27), 0 };
191 const arch_register_req_t sparc_single_reg_req_fp_f27 = {
192  .cls = &sparc_reg_classes[CLASS_sparc_fp],
193  .limited = sparc_limited_fp_f27,
194  .width = 1,
195 };
196 static const unsigned sparc_limited_fp_f28[] = { (1U << REG_FP_F28), 0 };
197 const arch_register_req_t sparc_single_reg_req_fp_f28 = {
198  .cls = &sparc_reg_classes[CLASS_sparc_fp],
199  .limited = sparc_limited_fp_f28,
200  .width = 1,
201 };
202 static const unsigned sparc_limited_fp_f29[] = { (1U << REG_FP_F29), 0 };
203 const arch_register_req_t sparc_single_reg_req_fp_f29 = {
204  .cls = &sparc_reg_classes[CLASS_sparc_fp],
205  .limited = sparc_limited_fp_f29,
206  .width = 1,
207 };
208 static const unsigned sparc_limited_fp_f30[] = { (1U << REG_FP_F30), 0 };
209 const arch_register_req_t sparc_single_reg_req_fp_f30 = {
210  .cls = &sparc_reg_classes[CLASS_sparc_fp],
211  .limited = sparc_limited_fp_f30,
212  .width = 1,
213 };
214 static const unsigned sparc_limited_fp_f31[] = { (1U << REG_FP_F31), 0 };
215 const arch_register_req_t sparc_single_reg_req_fp_f31 = {
216  .cls = &sparc_reg_classes[CLASS_sparc_fp],
217  .limited = sparc_limited_fp_f31,
218  .width = 1,
219 };
220 const arch_register_req_t sparc_class_reg_req_fpflags = {
221  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
222  .width = 1,
223 };
224 static const unsigned sparc_limited_fpflags_fsr[] = { (1U << REG_FPFLAGS_FSR) };
225 const arch_register_req_t sparc_single_reg_req_fpflags_fsr = {
226  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
227  .limited = sparc_limited_fpflags_fsr,
228  .width = 1,
229 };
230 const arch_register_req_t sparc_class_reg_req_gp = {
231  .cls = &sparc_reg_classes[CLASS_sparc_gp],
232  .width = 1,
233 };
234 static const unsigned sparc_limited_gp_l0[] = { (1U << REG_GP_L0), 0 };
235 const arch_register_req_t sparc_single_reg_req_gp_l0 = {
236  .cls = &sparc_reg_classes[CLASS_sparc_gp],
237  .limited = sparc_limited_gp_l0,
238  .width = 1,
239 };
240 static const unsigned sparc_limited_gp_l1[] = { (1U << REG_GP_L1), 0 };
241 const arch_register_req_t sparc_single_reg_req_gp_l1 = {
242  .cls = &sparc_reg_classes[CLASS_sparc_gp],
243  .limited = sparc_limited_gp_l1,
244  .width = 1,
245 };
246 static const unsigned sparc_limited_gp_l2[] = { (1U << REG_GP_L2), 0 };
247 const arch_register_req_t sparc_single_reg_req_gp_l2 = {
248  .cls = &sparc_reg_classes[CLASS_sparc_gp],
249  .limited = sparc_limited_gp_l2,
250  .width = 1,
251 };
252 static const unsigned sparc_limited_gp_l3[] = { (1U << REG_GP_L3), 0 };
253 const arch_register_req_t sparc_single_reg_req_gp_l3 = {
254  .cls = &sparc_reg_classes[CLASS_sparc_gp],
255  .limited = sparc_limited_gp_l3,
256  .width = 1,
257 };
258 static const unsigned sparc_limited_gp_l4[] = { (1U << REG_GP_L4), 0 };
259 const arch_register_req_t sparc_single_reg_req_gp_l4 = {
260  .cls = &sparc_reg_classes[CLASS_sparc_gp],
261  .limited = sparc_limited_gp_l4,
262  .width = 1,
263 };
264 static const unsigned sparc_limited_gp_l5[] = { (1U << REG_GP_L5), 0 };
265 const arch_register_req_t sparc_single_reg_req_gp_l5 = {
266  .cls = &sparc_reg_classes[CLASS_sparc_gp],
267  .limited = sparc_limited_gp_l5,
268  .width = 1,
269 };
270 static const unsigned sparc_limited_gp_l6[] = { (1U << REG_GP_L6), 0 };
271 const arch_register_req_t sparc_single_reg_req_gp_l6 = {
272  .cls = &sparc_reg_classes[CLASS_sparc_gp],
273  .limited = sparc_limited_gp_l6,
274  .width = 1,
275 };
276 static const unsigned sparc_limited_gp_l7[] = { (1U << REG_GP_L7), 0 };
277 const arch_register_req_t sparc_single_reg_req_gp_l7 = {
278  .cls = &sparc_reg_classes[CLASS_sparc_gp],
279  .limited = sparc_limited_gp_l7,
280  .width = 1,
281 };
282 static const unsigned sparc_limited_gp_g0[] = { (1U << REG_GP_G0), 0 };
283 const arch_register_req_t sparc_single_reg_req_gp_g0 = {
284  .cls = &sparc_reg_classes[CLASS_sparc_gp],
285  .limited = sparc_limited_gp_g0,
286  .width = 1,
287 };
288 static const unsigned sparc_limited_gp_g1[] = { (1U << REG_GP_G1), 0 };
289 const arch_register_req_t sparc_single_reg_req_gp_g1 = {
290  .cls = &sparc_reg_classes[CLASS_sparc_gp],
291  .limited = sparc_limited_gp_g1,
292  .width = 1,
293 };
294 static const unsigned sparc_limited_gp_g2[] = { (1U << REG_GP_G2), 0 };
295 const arch_register_req_t sparc_single_reg_req_gp_g2 = {
296  .cls = &sparc_reg_classes[CLASS_sparc_gp],
297  .limited = sparc_limited_gp_g2,
298  .width = 1,
299 };
300 static const unsigned sparc_limited_gp_g3[] = { (1U << REG_GP_G3), 0 };
301 const arch_register_req_t sparc_single_reg_req_gp_g3 = {
302  .cls = &sparc_reg_classes[CLASS_sparc_gp],
303  .limited = sparc_limited_gp_g3,
304  .width = 1,
305 };
306 static const unsigned sparc_limited_gp_g4[] = { (1U << REG_GP_G4), 0 };
307 const arch_register_req_t sparc_single_reg_req_gp_g4 = {
308  .cls = &sparc_reg_classes[CLASS_sparc_gp],
309  .limited = sparc_limited_gp_g4,
310  .width = 1,
311 };
312 static const unsigned sparc_limited_gp_g5[] = { (1U << REG_GP_G5), 0 };
313 const arch_register_req_t sparc_single_reg_req_gp_g5 = {
314  .cls = &sparc_reg_classes[CLASS_sparc_gp],
315  .limited = sparc_limited_gp_g5,
316  .width = 1,
317 };
318 static const unsigned sparc_limited_gp_g6[] = { (1U << REG_GP_G6), 0 };
319 const arch_register_req_t sparc_single_reg_req_gp_g6 = {
320  .cls = &sparc_reg_classes[CLASS_sparc_gp],
321  .limited = sparc_limited_gp_g6,
322  .width = 1,
323 };
324 static const unsigned sparc_limited_gp_g7[] = { (1U << REG_GP_G7), 0 };
325 const arch_register_req_t sparc_single_reg_req_gp_g7 = {
326  .cls = &sparc_reg_classes[CLASS_sparc_gp],
327  .limited = sparc_limited_gp_g7,
328  .width = 1,
329 };
330 static const unsigned sparc_limited_gp_o0[] = { (1U << REG_GP_O0), 0 };
331 const arch_register_req_t sparc_single_reg_req_gp_o0 = {
332  .cls = &sparc_reg_classes[CLASS_sparc_gp],
333  .limited = sparc_limited_gp_o0,
334  .width = 1,
335 };
336 static const unsigned sparc_limited_gp_o1[] = { (1U << REG_GP_O1), 0 };
337 const arch_register_req_t sparc_single_reg_req_gp_o1 = {
338  .cls = &sparc_reg_classes[CLASS_sparc_gp],
339  .limited = sparc_limited_gp_o1,
340  .width = 1,
341 };
342 static const unsigned sparc_limited_gp_o2[] = { (1U << REG_GP_O2), 0 };
343 const arch_register_req_t sparc_single_reg_req_gp_o2 = {
344  .cls = &sparc_reg_classes[CLASS_sparc_gp],
345  .limited = sparc_limited_gp_o2,
346  .width = 1,
347 };
348 static const unsigned sparc_limited_gp_o3[] = { (1U << REG_GP_O3), 0 };
349 const arch_register_req_t sparc_single_reg_req_gp_o3 = {
350  .cls = &sparc_reg_classes[CLASS_sparc_gp],
351  .limited = sparc_limited_gp_o3,
352  .width = 1,
353 };
354 static const unsigned sparc_limited_gp_o4[] = { (1U << REG_GP_O4), 0 };
355 const arch_register_req_t sparc_single_reg_req_gp_o4 = {
356  .cls = &sparc_reg_classes[CLASS_sparc_gp],
357  .limited = sparc_limited_gp_o4,
358  .width = 1,
359 };
360 static const unsigned sparc_limited_gp_o5[] = { (1U << REG_GP_O5), 0 };
361 const arch_register_req_t sparc_single_reg_req_gp_o5 = {
362  .cls = &sparc_reg_classes[CLASS_sparc_gp],
363  .limited = sparc_limited_gp_o5,
364  .width = 1,
365 };
366 static const unsigned sparc_limited_gp_sp[] = { (1U << REG_GP_SP), 0 };
367 const arch_register_req_t sparc_single_reg_req_gp_sp = {
368  .cls = &sparc_reg_classes[CLASS_sparc_gp],
369  .limited = sparc_limited_gp_sp,
370  .width = 1,
371 };
372 static const unsigned sparc_limited_gp_o7[] = { (1U << REG_GP_O7), 0 };
373 const arch_register_req_t sparc_single_reg_req_gp_o7 = {
374  .cls = &sparc_reg_classes[CLASS_sparc_gp],
375  .limited = sparc_limited_gp_o7,
376  .width = 1,
377 };
378 static const unsigned sparc_limited_gp_i0[] = { (1U << REG_GP_I0), 0 };
379 const arch_register_req_t sparc_single_reg_req_gp_i0 = {
380  .cls = &sparc_reg_classes[CLASS_sparc_gp],
381  .limited = sparc_limited_gp_i0,
382  .width = 1,
383 };
384 static const unsigned sparc_limited_gp_i1[] = { (1U << REG_GP_I1), 0 };
385 const arch_register_req_t sparc_single_reg_req_gp_i1 = {
386  .cls = &sparc_reg_classes[CLASS_sparc_gp],
387  .limited = sparc_limited_gp_i1,
388  .width = 1,
389 };
390 static const unsigned sparc_limited_gp_i2[] = { (1U << REG_GP_I2), 0 };
391 const arch_register_req_t sparc_single_reg_req_gp_i2 = {
392  .cls = &sparc_reg_classes[CLASS_sparc_gp],
393  .limited = sparc_limited_gp_i2,
394  .width = 1,
395 };
396 static const unsigned sparc_limited_gp_i3[] = { (1U << REG_GP_I3), 0 };
397 const arch_register_req_t sparc_single_reg_req_gp_i3 = {
398  .cls = &sparc_reg_classes[CLASS_sparc_gp],
399  .limited = sparc_limited_gp_i3,
400  .width = 1,
401 };
402 static const unsigned sparc_limited_gp_i4[] = { (1U << REG_GP_I4), 0 };
403 const arch_register_req_t sparc_single_reg_req_gp_i4 = {
404  .cls = &sparc_reg_classes[CLASS_sparc_gp],
405  .limited = sparc_limited_gp_i4,
406  .width = 1,
407 };
408 static const unsigned sparc_limited_gp_i5[] = { (1U << REG_GP_I5), 0 };
409 const arch_register_req_t sparc_single_reg_req_gp_i5 = {
410  .cls = &sparc_reg_classes[CLASS_sparc_gp],
411  .limited = sparc_limited_gp_i5,
412  .width = 1,
413 };
414 static const unsigned sparc_limited_gp_fp[] = { (1U << REG_GP_FP), 0 };
415 const arch_register_req_t sparc_single_reg_req_gp_fp = {
416  .cls = &sparc_reg_classes[CLASS_sparc_gp],
417  .limited = sparc_limited_gp_fp,
418  .width = 1,
419 };
420 static const unsigned sparc_limited_gp_i7[] = { (1U << REG_GP_I7), 0 };
421 const arch_register_req_t sparc_single_reg_req_gp_i7 = {
422  .cls = &sparc_reg_classes[CLASS_sparc_gp],
423  .limited = sparc_limited_gp_i7,
424  .width = 1,
425 };
426 const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
427  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
428  .width = 1,
429 };
430 static const unsigned sparc_limited_mul_div_high_res_y[] = { (1U << REG_MUL_DIV_HIGH_RES_Y) };
431 const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
432  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
433  .limited = sparc_limited_mul_div_high_res_y,
434  .width = 1,
435 };
436 
437 
438 arch_register_class_t sparc_reg_classes[] = {
439  {
440  .name = "sparc_flags",
441  .mode = NULL,
442  .regs = &sparc_registers[REG_PSR],
443  .class_req = &sparc_class_reg_req_flags,
444  .index = CLASS_sparc_flags,
445  .n_regs = 1,
446  .manual_ra = true,
447  },
448  {
449  .name = "sparc_fp",
450  .mode = NULL,
451  .regs = &sparc_registers[REG_F0],
452  .class_req = &sparc_class_reg_req_fp,
453  .index = CLASS_sparc_fp,
454  .n_regs = 32,
455  .manual_ra = false,
456  },
457  {
458  .name = "sparc_fpflags",
459  .mode = NULL,
460  .regs = &sparc_registers[REG_FSR],
461  .class_req = &sparc_class_reg_req_fpflags,
462  .index = CLASS_sparc_fpflags,
463  .n_regs = 1,
464  .manual_ra = true,
465  },
466  {
467  .name = "sparc_gp",
468  .mode = NULL,
469  .regs = &sparc_registers[REG_L0],
470  .class_req = &sparc_class_reg_req_gp,
471  .index = CLASS_sparc_gp,
472  .n_regs = 32,
473  .manual_ra = false,
474  },
475  {
476  .name = "sparc_mul_div_high_res",
477  .mode = NULL,
478  .regs = &sparc_registers[REG_Y],
479  .class_req = &sparc_class_reg_req_mul_div_high_res,
480  .index = CLASS_sparc_mul_div_high_res,
481  .n_regs = 1,
482  .manual_ra = true,
483  },
484 
485 };
486 
488 const arch_register_t sparc_registers[] = {
489  {
490  .name = "psr",
491  .cls = &sparc_reg_classes[CLASS_sparc_flags],
492  .single_req = &sparc_single_reg_req_flags_psr,
493  .index = REG_FLAGS_PSR,
494  .global_index = REG_PSR,
495  .dwarf_number = 0,
496  .encoding = REG_FLAGS_PSR,
497  .is_virtual = false,
498  },
499  {
500  .name = "f0",
501  .cls = &sparc_reg_classes[CLASS_sparc_fp],
502  .single_req = &sparc_single_reg_req_fp_f0,
503  .index = REG_FP_F0,
504  .global_index = REG_F0,
505  .dwarf_number = 32,
506  .encoding = 0,
507  .is_virtual = false,
508  },
509  {
510  .name = "f1",
511  .cls = &sparc_reg_classes[CLASS_sparc_fp],
512  .single_req = &sparc_single_reg_req_fp_f1,
513  .index = REG_FP_F1,
514  .global_index = REG_F1,
515  .dwarf_number = 33,
516  .encoding = 1,
517  .is_virtual = false,
518  },
519  {
520  .name = "f2",
521  .cls = &sparc_reg_classes[CLASS_sparc_fp],
522  .single_req = &sparc_single_reg_req_fp_f2,
523  .index = REG_FP_F2,
524  .global_index = REG_F2,
525  .dwarf_number = 34,
526  .encoding = 2,
527  .is_virtual = false,
528  },
529  {
530  .name = "f3",
531  .cls = &sparc_reg_classes[CLASS_sparc_fp],
532  .single_req = &sparc_single_reg_req_fp_f3,
533  .index = REG_FP_F3,
534  .global_index = REG_F3,
535  .dwarf_number = 35,
536  .encoding = 3,
537  .is_virtual = false,
538  },
539  {
540  .name = "f4",
541  .cls = &sparc_reg_classes[CLASS_sparc_fp],
542  .single_req = &sparc_single_reg_req_fp_f4,
543  .index = REG_FP_F4,
544  .global_index = REG_F4,
545  .dwarf_number = 36,
546  .encoding = 4,
547  .is_virtual = false,
548  },
549  {
550  .name = "f5",
551  .cls = &sparc_reg_classes[CLASS_sparc_fp],
552  .single_req = &sparc_single_reg_req_fp_f5,
553  .index = REG_FP_F5,
554  .global_index = REG_F5,
555  .dwarf_number = 37,
556  .encoding = 5,
557  .is_virtual = false,
558  },
559  {
560  .name = "f6",
561  .cls = &sparc_reg_classes[CLASS_sparc_fp],
562  .single_req = &sparc_single_reg_req_fp_f6,
563  .index = REG_FP_F6,
564  .global_index = REG_F6,
565  .dwarf_number = 38,
566  .encoding = 6,
567  .is_virtual = false,
568  },
569  {
570  .name = "f7",
571  .cls = &sparc_reg_classes[CLASS_sparc_fp],
572  .single_req = &sparc_single_reg_req_fp_f7,
573  .index = REG_FP_F7,
574  .global_index = REG_F7,
575  .dwarf_number = 39,
576  .encoding = 7,
577  .is_virtual = false,
578  },
579  {
580  .name = "f8",
581  .cls = &sparc_reg_classes[CLASS_sparc_fp],
582  .single_req = &sparc_single_reg_req_fp_f8,
583  .index = REG_FP_F8,
584  .global_index = REG_F8,
585  .dwarf_number = 40,
586  .encoding = 8,
587  .is_virtual = false,
588  },
589  {
590  .name = "f9",
591  .cls = &sparc_reg_classes[CLASS_sparc_fp],
592  .single_req = &sparc_single_reg_req_fp_f9,
593  .index = REG_FP_F9,
594  .global_index = REG_F9,
595  .dwarf_number = 41,
596  .encoding = 9,
597  .is_virtual = false,
598  },
599  {
600  .name = "f10",
601  .cls = &sparc_reg_classes[CLASS_sparc_fp],
602  .single_req = &sparc_single_reg_req_fp_f10,
603  .index = REG_FP_F10,
604  .global_index = REG_F10,
605  .dwarf_number = 42,
606  .encoding = 10,
607  .is_virtual = false,
608  },
609  {
610  .name = "f11",
611  .cls = &sparc_reg_classes[CLASS_sparc_fp],
612  .single_req = &sparc_single_reg_req_fp_f11,
613  .index = REG_FP_F11,
614  .global_index = REG_F11,
615  .dwarf_number = 43,
616  .encoding = 11,
617  .is_virtual = false,
618  },
619  {
620  .name = "f12",
621  .cls = &sparc_reg_classes[CLASS_sparc_fp],
622  .single_req = &sparc_single_reg_req_fp_f12,
623  .index = REG_FP_F12,
624  .global_index = REG_F12,
625  .dwarf_number = 44,
626  .encoding = 12,
627  .is_virtual = false,
628  },
629  {
630  .name = "f13",
631  .cls = &sparc_reg_classes[CLASS_sparc_fp],
632  .single_req = &sparc_single_reg_req_fp_f13,
633  .index = REG_FP_F13,
634  .global_index = REG_F13,
635  .dwarf_number = 45,
636  .encoding = 13,
637  .is_virtual = false,
638  },
639  {
640  .name = "f14",
641  .cls = &sparc_reg_classes[CLASS_sparc_fp],
642  .single_req = &sparc_single_reg_req_fp_f14,
643  .index = REG_FP_F14,
644  .global_index = REG_F14,
645  .dwarf_number = 46,
646  .encoding = 14,
647  .is_virtual = false,
648  },
649  {
650  .name = "f15",
651  .cls = &sparc_reg_classes[CLASS_sparc_fp],
652  .single_req = &sparc_single_reg_req_fp_f15,
653  .index = REG_FP_F15,
654  .global_index = REG_F15,
655  .dwarf_number = 47,
656  .encoding = 15,
657  .is_virtual = false,
658  },
659  {
660  .name = "f16",
661  .cls = &sparc_reg_classes[CLASS_sparc_fp],
662  .single_req = &sparc_single_reg_req_fp_f16,
663  .index = REG_FP_F16,
664  .global_index = REG_F16,
665  .dwarf_number = 48,
666  .encoding = 16,
667  .is_virtual = false,
668  },
669  {
670  .name = "f17",
671  .cls = &sparc_reg_classes[CLASS_sparc_fp],
672  .single_req = &sparc_single_reg_req_fp_f17,
673  .index = REG_FP_F17,
674  .global_index = REG_F17,
675  .dwarf_number = 49,
676  .encoding = 17,
677  .is_virtual = false,
678  },
679  {
680  .name = "f18",
681  .cls = &sparc_reg_classes[CLASS_sparc_fp],
682  .single_req = &sparc_single_reg_req_fp_f18,
683  .index = REG_FP_F18,
684  .global_index = REG_F18,
685  .dwarf_number = 50,
686  .encoding = 18,
687  .is_virtual = false,
688  },
689  {
690  .name = "f19",
691  .cls = &sparc_reg_classes[CLASS_sparc_fp],
692  .single_req = &sparc_single_reg_req_fp_f19,
693  .index = REG_FP_F19,
694  .global_index = REG_F19,
695  .dwarf_number = 51,
696  .encoding = 19,
697  .is_virtual = false,
698  },
699  {
700  .name = "f20",
701  .cls = &sparc_reg_classes[CLASS_sparc_fp],
702  .single_req = &sparc_single_reg_req_fp_f20,
703  .index = REG_FP_F20,
704  .global_index = REG_F20,
705  .dwarf_number = 52,
706  .encoding = 20,
707  .is_virtual = false,
708  },
709  {
710  .name = "f21",
711  .cls = &sparc_reg_classes[CLASS_sparc_fp],
712  .single_req = &sparc_single_reg_req_fp_f21,
713  .index = REG_FP_F21,
714  .global_index = REG_F21,
715  .dwarf_number = 53,
716  .encoding = 21,
717  .is_virtual = false,
718  },
719  {
720  .name = "f22",
721  .cls = &sparc_reg_classes[CLASS_sparc_fp],
722  .single_req = &sparc_single_reg_req_fp_f22,
723  .index = REG_FP_F22,
724  .global_index = REG_F22,
725  .dwarf_number = 54,
726  .encoding = 22,
727  .is_virtual = false,
728  },
729  {
730  .name = "f23",
731  .cls = &sparc_reg_classes[CLASS_sparc_fp],
732  .single_req = &sparc_single_reg_req_fp_f23,
733  .index = REG_FP_F23,
734  .global_index = REG_F23,
735  .dwarf_number = 55,
736  .encoding = 23,
737  .is_virtual = false,
738  },
739  {
740  .name = "f24",
741  .cls = &sparc_reg_classes[CLASS_sparc_fp],
742  .single_req = &sparc_single_reg_req_fp_f24,
743  .index = REG_FP_F24,
744  .global_index = REG_F24,
745  .dwarf_number = 56,
746  .encoding = 24,
747  .is_virtual = false,
748  },
749  {
750  .name = "f25",
751  .cls = &sparc_reg_classes[CLASS_sparc_fp],
752  .single_req = &sparc_single_reg_req_fp_f25,
753  .index = REG_FP_F25,
754  .global_index = REG_F25,
755  .dwarf_number = 57,
756  .encoding = 25,
757  .is_virtual = false,
758  },
759  {
760  .name = "f26",
761  .cls = &sparc_reg_classes[CLASS_sparc_fp],
762  .single_req = &sparc_single_reg_req_fp_f26,
763  .index = REG_FP_F26,
764  .global_index = REG_F26,
765  .dwarf_number = 58,
766  .encoding = 26,
767  .is_virtual = false,
768  },
769  {
770  .name = "f27",
771  .cls = &sparc_reg_classes[CLASS_sparc_fp],
772  .single_req = &sparc_single_reg_req_fp_f27,
773  .index = REG_FP_F27,
774  .global_index = REG_F27,
775  .dwarf_number = 59,
776  .encoding = 27,
777  .is_virtual = false,
778  },
779  {
780  .name = "f28",
781  .cls = &sparc_reg_classes[CLASS_sparc_fp],
782  .single_req = &sparc_single_reg_req_fp_f28,
783  .index = REG_FP_F28,
784  .global_index = REG_F28,
785  .dwarf_number = 60,
786  .encoding = 28,
787  .is_virtual = false,
788  },
789  {
790  .name = "f29",
791  .cls = &sparc_reg_classes[CLASS_sparc_fp],
792  .single_req = &sparc_single_reg_req_fp_f29,
793  .index = REG_FP_F29,
794  .global_index = REG_F29,
795  .dwarf_number = 61,
796  .encoding = 29,
797  .is_virtual = false,
798  },
799  {
800  .name = "f30",
801  .cls = &sparc_reg_classes[CLASS_sparc_fp],
802  .single_req = &sparc_single_reg_req_fp_f30,
803  .index = REG_FP_F30,
804  .global_index = REG_F30,
805  .dwarf_number = 62,
806  .encoding = 30,
807  .is_virtual = false,
808  },
809  {
810  .name = "f31",
811  .cls = &sparc_reg_classes[CLASS_sparc_fp],
812  .single_req = &sparc_single_reg_req_fp_f31,
813  .index = REG_FP_F31,
814  .global_index = REG_F31,
815  .dwarf_number = 63,
816  .encoding = 31,
817  .is_virtual = false,
818  },
819  {
820  .name = "fsr",
821  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
822  .single_req = &sparc_single_reg_req_fpflags_fsr,
823  .index = REG_FPFLAGS_FSR,
824  .global_index = REG_FSR,
825  .dwarf_number = 0,
826  .encoding = REG_FPFLAGS_FSR,
827  .is_virtual = false,
828  },
829  {
830  .name = "l0",
831  .cls = &sparc_reg_classes[CLASS_sparc_gp],
832  .single_req = &sparc_single_reg_req_gp_l0,
833  .index = REG_GP_L0,
834  .global_index = REG_L0,
835  .dwarf_number = 16,
836  .encoding = 16,
837  .is_virtual = false,
838  },
839  {
840  .name = "l1",
841  .cls = &sparc_reg_classes[CLASS_sparc_gp],
842  .single_req = &sparc_single_reg_req_gp_l1,
843  .index = REG_GP_L1,
844  .global_index = REG_L1,
845  .dwarf_number = 17,
846  .encoding = 17,
847  .is_virtual = false,
848  },
849  {
850  .name = "l2",
851  .cls = &sparc_reg_classes[CLASS_sparc_gp],
852  .single_req = &sparc_single_reg_req_gp_l2,
853  .index = REG_GP_L2,
854  .global_index = REG_L2,
855  .dwarf_number = 18,
856  .encoding = 18,
857  .is_virtual = false,
858  },
859  {
860  .name = "l3",
861  .cls = &sparc_reg_classes[CLASS_sparc_gp],
862  .single_req = &sparc_single_reg_req_gp_l3,
863  .index = REG_GP_L3,
864  .global_index = REG_L3,
865  .dwarf_number = 19,
866  .encoding = 19,
867  .is_virtual = false,
868  },
869  {
870  .name = "l4",
871  .cls = &sparc_reg_classes[CLASS_sparc_gp],
872  .single_req = &sparc_single_reg_req_gp_l4,
873  .index = REG_GP_L4,
874  .global_index = REG_L4,
875  .dwarf_number = 20,
876  .encoding = 20,
877  .is_virtual = false,
878  },
879  {
880  .name = "l5",
881  .cls = &sparc_reg_classes[CLASS_sparc_gp],
882  .single_req = &sparc_single_reg_req_gp_l5,
883  .index = REG_GP_L5,
884  .global_index = REG_L5,
885  .dwarf_number = 21,
886  .encoding = 21,
887  .is_virtual = false,
888  },
889  {
890  .name = "l6",
891  .cls = &sparc_reg_classes[CLASS_sparc_gp],
892  .single_req = &sparc_single_reg_req_gp_l6,
893  .index = REG_GP_L6,
894  .global_index = REG_L6,
895  .dwarf_number = 22,
896  .encoding = 22,
897  .is_virtual = false,
898  },
899  {
900  .name = "l7",
901  .cls = &sparc_reg_classes[CLASS_sparc_gp],
902  .single_req = &sparc_single_reg_req_gp_l7,
903  .index = REG_GP_L7,
904  .global_index = REG_L7,
905  .dwarf_number = 23,
906  .encoding = 23,
907  .is_virtual = false,
908  },
909  {
910  .name = "g0",
911  .cls = &sparc_reg_classes[CLASS_sparc_gp],
912  .single_req = &sparc_single_reg_req_gp_g0,
913  .index = REG_GP_G0,
914  .global_index = REG_G0,
915  .dwarf_number = 0,
916  .encoding = 0,
917  .is_virtual = false,
918  },
919  {
920  .name = "g1",
921  .cls = &sparc_reg_classes[CLASS_sparc_gp],
922  .single_req = &sparc_single_reg_req_gp_g1,
923  .index = REG_GP_G1,
924  .global_index = REG_G1,
925  .dwarf_number = 1,
926  .encoding = 1,
927  .is_virtual = false,
928  },
929  {
930  .name = "g2",
931  .cls = &sparc_reg_classes[CLASS_sparc_gp],
932  .single_req = &sparc_single_reg_req_gp_g2,
933  .index = REG_GP_G2,
934  .global_index = REG_G2,
935  .dwarf_number = 2,
936  .encoding = 2,
937  .is_virtual = false,
938  },
939  {
940  .name = "g3",
941  .cls = &sparc_reg_classes[CLASS_sparc_gp],
942  .single_req = &sparc_single_reg_req_gp_g3,
943  .index = REG_GP_G3,
944  .global_index = REG_G3,
945  .dwarf_number = 3,
946  .encoding = 3,
947  .is_virtual = false,
948  },
949  {
950  .name = "g4",
951  .cls = &sparc_reg_classes[CLASS_sparc_gp],
952  .single_req = &sparc_single_reg_req_gp_g4,
953  .index = REG_GP_G4,
954  .global_index = REG_G4,
955  .dwarf_number = 4,
956  .encoding = 4,
957  .is_virtual = false,
958  },
959  {
960  .name = "g5",
961  .cls = &sparc_reg_classes[CLASS_sparc_gp],
962  .single_req = &sparc_single_reg_req_gp_g5,
963  .index = REG_GP_G5,
964  .global_index = REG_G5,
965  .dwarf_number = 5,
966  .encoding = 5,
967  .is_virtual = false,
968  },
969  {
970  .name = "g6",
971  .cls = &sparc_reg_classes[CLASS_sparc_gp],
972  .single_req = &sparc_single_reg_req_gp_g6,
973  .index = REG_GP_G6,
974  .global_index = REG_G6,
975  .dwarf_number = 6,
976  .encoding = 6,
977  .is_virtual = false,
978  },
979  {
980  .name = "g7",
981  .cls = &sparc_reg_classes[CLASS_sparc_gp],
982  .single_req = &sparc_single_reg_req_gp_g7,
983  .index = REG_GP_G7,
984  .global_index = REG_G7,
985  .dwarf_number = 7,
986  .encoding = 7,
987  .is_virtual = false,
988  },
989  {
990  .name = "o0",
991  .cls = &sparc_reg_classes[CLASS_sparc_gp],
992  .single_req = &sparc_single_reg_req_gp_o0,
993  .index = REG_GP_O0,
994  .global_index = REG_O0,
995  .dwarf_number = 8,
996  .encoding = 8,
997  .is_virtual = false,
998  },
999  {
1000  .name = "o1",
1001  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1002  .single_req = &sparc_single_reg_req_gp_o1,
1003  .index = REG_GP_O1,
1004  .global_index = REG_O1,
1005  .dwarf_number = 9,
1006  .encoding = 9,
1007  .is_virtual = false,
1008  },
1009  {
1010  .name = "o2",
1011  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1012  .single_req = &sparc_single_reg_req_gp_o2,
1013  .index = REG_GP_O2,
1014  .global_index = REG_O2,
1015  .dwarf_number = 10,
1016  .encoding = 10,
1017  .is_virtual = false,
1018  },
1019  {
1020  .name = "o3",
1021  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1022  .single_req = &sparc_single_reg_req_gp_o3,
1023  .index = REG_GP_O3,
1024  .global_index = REG_O3,
1025  .dwarf_number = 11,
1026  .encoding = 11,
1027  .is_virtual = false,
1028  },
1029  {
1030  .name = "o4",
1031  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1032  .single_req = &sparc_single_reg_req_gp_o4,
1033  .index = REG_GP_O4,
1034  .global_index = REG_O4,
1035  .dwarf_number = 12,
1036  .encoding = 12,
1037  .is_virtual = false,
1038  },
1039  {
1040  .name = "o5",
1041  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1042  .single_req = &sparc_single_reg_req_gp_o5,
1043  .index = REG_GP_O5,
1044  .global_index = REG_O5,
1045  .dwarf_number = 13,
1046  .encoding = 13,
1047  .is_virtual = false,
1048  },
1049  {
1050  .name = "sp",
1051  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1052  .single_req = &sparc_single_reg_req_gp_sp,
1053  .index = REG_GP_SP,
1054  .global_index = REG_SP,
1055  .dwarf_number = 14,
1056  .encoding = 14,
1057  .is_virtual = false,
1058  },
1059  {
1060  .name = "o7",
1061  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1062  .single_req = &sparc_single_reg_req_gp_o7,
1063  .index = REG_GP_O7,
1064  .global_index = REG_O7,
1065  .dwarf_number = 15,
1066  .encoding = 15,
1067  .is_virtual = false,
1068  },
1069  {
1070  .name = "i0",
1071  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1072  .single_req = &sparc_single_reg_req_gp_i0,
1073  .index = REG_GP_I0,
1074  .global_index = REG_I0,
1075  .dwarf_number = 24,
1076  .encoding = 24,
1077  .is_virtual = false,
1078  },
1079  {
1080  .name = "i1",
1081  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1082  .single_req = &sparc_single_reg_req_gp_i1,
1083  .index = REG_GP_I1,
1084  .global_index = REG_I1,
1085  .dwarf_number = 25,
1086  .encoding = 25,
1087  .is_virtual = false,
1088  },
1089  {
1090  .name = "i2",
1091  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1092  .single_req = &sparc_single_reg_req_gp_i2,
1093  .index = REG_GP_I2,
1094  .global_index = REG_I2,
1095  .dwarf_number = 26,
1096  .encoding = 26,
1097  .is_virtual = false,
1098  },
1099  {
1100  .name = "i3",
1101  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1102  .single_req = &sparc_single_reg_req_gp_i3,
1103  .index = REG_GP_I3,
1104  .global_index = REG_I3,
1105  .dwarf_number = 27,
1106  .encoding = 27,
1107  .is_virtual = false,
1108  },
1109  {
1110  .name = "i4",
1111  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1112  .single_req = &sparc_single_reg_req_gp_i4,
1113  .index = REG_GP_I4,
1114  .global_index = REG_I4,
1115  .dwarf_number = 28,
1116  .encoding = 28,
1117  .is_virtual = false,
1118  },
1119  {
1120  .name = "i5",
1121  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1122  .single_req = &sparc_single_reg_req_gp_i5,
1123  .index = REG_GP_I5,
1124  .global_index = REG_I5,
1125  .dwarf_number = 29,
1126  .encoding = 29,
1127  .is_virtual = false,
1128  },
1129  {
1130  .name = "fp",
1131  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1132  .single_req = &sparc_single_reg_req_gp_fp,
1133  .index = REG_GP_FP,
1134  .global_index = REG_FP,
1135  .dwarf_number = 30,
1136  .encoding = 30,
1137  .is_virtual = false,
1138  },
1139  {
1140  .name = "i7",
1141  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1142  .single_req = &sparc_single_reg_req_gp_i7,
1143  .index = REG_GP_I7,
1144  .global_index = REG_I7,
1145  .dwarf_number = 31,
1146  .encoding = 31,
1147  .is_virtual = false,
1148  },
1149  {
1150  .name = "y",
1151  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1152  .single_req = &sparc_single_reg_req_mul_div_high_res_y,
1153  .index = REG_MUL_DIV_HIGH_RES_Y,
1154  .global_index = REG_Y,
1155  .dwarf_number = 0,
1156  .encoding = REG_MUL_DIV_HIGH_RES_Y,
1157  .is_virtual = false,
1158  },
1159 
1160 };
1161 
1165 void sparc_register_init(void)
1166 {
1167  sparc_reg_classes[CLASS_sparc_flags].mode = mode_Bu;
1168  sparc_reg_classes[CLASS_sparc_fp].mode = mode_F;
1169  sparc_reg_classes[CLASS_sparc_fpflags].mode = mode_Bu;
1170  sparc_reg_classes[CLASS_sparc_gp].mode = mode_Iu;
1171  sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode = mode_Iu;
1172 
1173 }
ir_mode * mode_Bu
uint8
Definition: irmode.h:197
ir_mode * mode_Iu
uint32
Definition: irmode.h:201
ir_mode * mode_F
ieee754 binary32 float (single precision)
Definition: irmode.h:194