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gen_ia32_new_nodes.h
1 
9 #ifndef FIRM_BE_IA32_GEN_IA32_NEW_NODES_H
10 #define FIRM_BE_IA32_GEN_IA32_NEW_NODES_H
11 
12 #include "be_types.h"
13 #include "irnode_t.h"
14 
15 typedef enum ia32_opcodes {
16  iro_ia32_Adc,
17  iro_ia32_Add,
18  iro_ia32_AddMem,
19  iro_ia32_AddSP,
20  iro_ia32_And,
21  iro_ia32_AndMem,
22  iro_ia32_Breakpoint,
23  iro_ia32_Bsf,
24  iro_ia32_Bsr,
25  iro_ia32_Bswap,
26  iro_ia32_Bswap16,
27  iro_ia32_Bt,
28  iro_ia32_CMovcc,
29  iro_ia32_Call,
30  iro_ia32_ChangeCW,
31  iro_ia32_ClimbFrame,
32  iro_ia32_Cltd,
33  iro_ia32_Cmc,
34  iro_ia32_Cmp,
35  iro_ia32_CmpXChgMem,
36  iro_ia32_Const,
37  iro_ia32_Conv_FP2FP,
38  iro_ia32_Conv_FP2I,
39  iro_ia32_Conv_I2FP,
40  iro_ia32_Conv_I2I,
41  iro_ia32_CopyB,
42  iro_ia32_CopyB_i,
43  iro_ia32_CopyEbpEsp,
44  iro_ia32_CvtSI2SD,
45  iro_ia32_CvtSI2SS,
46  iro_ia32_Cwtl,
47  iro_ia32_Dec,
48  iro_ia32_DecMem,
49  iro_ia32_Div,
50  iro_ia32_Enter,
51  iro_ia32_FldCW,
52  iro_ia32_FnstCW,
53  iro_ia32_FnstCWNOP,
54  iro_ia32_FtstFnstsw,
55  iro_ia32_FucomFnstsw,
56  iro_ia32_Fucomi,
57  iro_ia32_FucomppFnstsw,
58  iro_ia32_GetEIP,
59  iro_ia32_IDiv,
60  iro_ia32_IJmp,
61  iro_ia32_IMul,
62  iro_ia32_IMul1OP,
63  iro_ia32_IMulImm,
64  iro_ia32_Immediate,
65  iro_ia32_Inc,
66  iro_ia32_IncMem,
67  iro_ia32_Inport,
68  iro_ia32_Jcc,
69  iro_ia32_Jmp,
70  iro_ia32_LdTls,
71  iro_ia32_Lea,
72  iro_ia32_Leave,
73  iro_ia32_Load,
74  iro_ia32_Minus64,
75  iro_ia32_Mul,
76  iro_ia32_Neg,
77  iro_ia32_NegMem,
78  iro_ia32_NoReg_FP,
79  iro_ia32_NoReg_GP,
80  iro_ia32_NoReg_XMM,
81  iro_ia32_Not,
82  iro_ia32_NotMem,
83  iro_ia32_Or,
84  iro_ia32_OrMem,
85  iro_ia32_Outport,
86  iro_ia32_Pop,
87  iro_ia32_PopMem,
88  iro_ia32_Popcnt,
89  iro_ia32_Prefetch,
90  iro_ia32_Prefetch0,
91  iro_ia32_Prefetch1,
92  iro_ia32_Prefetch2,
93  iro_ia32_PrefetchNTA,
94  iro_ia32_PrefetchW,
95  iro_ia32_Push,
96  iro_ia32_PushEax,
97  iro_ia32_Return,
98  iro_ia32_Rol,
99  iro_ia32_RolMem,
100  iro_ia32_Ror,
101  iro_ia32_RorMem,
102  iro_ia32_Sahf,
103  iro_ia32_Sar,
104  iro_ia32_SarMem,
105  iro_ia32_Sbb,
106  iro_ia32_Sbb0,
107  iro_ia32_Setcc,
108  iro_ia32_SetccMem,
109  iro_ia32_Shl,
110  iro_ia32_ShlD,
111  iro_ia32_ShlMem,
112  iro_ia32_Shr,
113  iro_ia32_ShrD,
114  iro_ia32_ShrMem,
115  iro_ia32_Stc,
116  iro_ia32_Store,
117  iro_ia32_Sub,
118  iro_ia32_SubMem,
119  iro_ia32_SubSP,
120  iro_ia32_SwitchJmp,
121  iro_ia32_Test,
122  iro_ia32_UD2,
123  iro_ia32_Ucomi,
124  iro_ia32_Unknown,
125  iro_ia32_Xor,
126  iro_ia32_Xor0,
127  iro_ia32_XorHighLow,
128  iro_ia32_XorMem,
129  iro_ia32_emms,
130  iro_ia32_fabs,
131  iro_ia32_fadd,
132  iro_ia32_fchs,
133  iro_ia32_fdiv,
134  iro_ia32_fdup,
135  iro_ia32_femms,
136  iro_ia32_ffreep,
137  iro_ia32_fild,
138  iro_ia32_fist,
139  iro_ia32_fistp,
140  iro_ia32_fisttp,
141  iro_ia32_fld,
142  iro_ia32_fld1,
143  iro_ia32_fldl2e,
144  iro_ia32_fldl2t,
145  iro_ia32_fldlg2,
146  iro_ia32_fldln2,
147  iro_ia32_fldpi,
148  iro_ia32_fldz,
149  iro_ia32_fmul,
150  iro_ia32_fpop,
151  iro_ia32_fst,
152  iro_ia32_fstp,
153  iro_ia32_fsub,
154  iro_ia32_fxch,
155  iro_ia32_l_Adc,
156  iro_ia32_l_Add,
157  iro_ia32_l_FloattoLL,
158  iro_ia32_l_IMul,
159  iro_ia32_l_LLtoFloat,
160  iro_ia32_l_Minus64,
161  iro_ia32_l_Mul,
162  iro_ia32_l_Sbb,
163  iro_ia32_l_Sub,
164  iro_ia32_xAdd,
165  iro_ia32_xAllOnes,
166  iro_ia32_xAnd,
167  iro_ia32_xAndNot,
168  iro_ia32_xDiv,
169  iro_ia32_xLoad,
170  iro_ia32_xMax,
171  iro_ia32_xMin,
172  iro_ia32_xMovd,
173  iro_ia32_xMul,
174  iro_ia32_xOr,
175  iro_ia32_xPslld,
176  iro_ia32_xPsllq,
177  iro_ia32_xPsrld,
178  iro_ia32_xPzero,
179  iro_ia32_xStore,
180  iro_ia32_xSub,
181  iro_ia32_xUnknown,
182  iro_ia32_xXor,
183  iro_ia32_xZero,
184  iro_ia32_xxLoad,
185  iro_ia32_xxStore,
186  iro_ia32_last
187 } ia32_opcodes;
188 
189 
190 int is_ia32_irn(const ir_node *node);
191 int is_ia32_op(const ir_op *op);
192 
193 int get_ia32_irn_opcode(const ir_node *node);
194 void ia32_create_opcodes(void);
195 void ia32_free_opcodes(void);
196 
197 extern ir_op *op_ia32_Adc;
198 
199 static inline bool is_ia32_Adc(ir_node const *const n)
200 {
201  return get_irn_op(n) == op_ia32_Adc;
202 }
203 
207 ir_node *new_bd_ia32_Adc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *eflags);
208 
209 extern ir_op *op_ia32_Add;
210 
211 static inline bool is_ia32_Add(ir_node const *const n)
212 {
213  return get_irn_op(n) == op_ia32_Add;
214 }
215 
219 ir_node *new_bd_ia32_Add(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
223 ir_node *new_bd_ia32_Add_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
224 
225 extern ir_op *op_ia32_AddMem;
226 
227 static inline bool is_ia32_AddMem(ir_node const *const n)
228 {
229  return get_irn_op(n) == op_ia32_AddMem;
230 }
231 
235 ir_node *new_bd_ia32_AddMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
239 ir_node *new_bd_ia32_AddMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
240 
241 extern ir_op *op_ia32_AddSP;
242 
243 static inline bool is_ia32_AddSP(ir_node const *const n)
244 {
245  return get_irn_op(n) == op_ia32_AddSP;
246 }
247 
251 ir_node *new_bd_ia32_AddSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *size);
252 
253 extern ir_op *op_ia32_And;
254 
255 static inline bool is_ia32_And(ir_node const *const n)
256 {
257  return get_irn_op(n) == op_ia32_And;
258 }
259 
263 ir_node *new_bd_ia32_And(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
267 ir_node *new_bd_ia32_And_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
268 
269 extern ir_op *op_ia32_AndMem;
270 
271 static inline bool is_ia32_AndMem(ir_node const *const n)
272 {
273  return get_irn_op(n) == op_ia32_AndMem;
274 }
275 
279 ir_node *new_bd_ia32_AndMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
283 ir_node *new_bd_ia32_AndMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
284 
285 extern ir_op *op_ia32_Breakpoint;
286 
287 static inline bool is_ia32_Breakpoint(ir_node const *const n)
288 {
289  return get_irn_op(n) == op_ia32_Breakpoint;
290 }
291 
295 ir_node *new_bd_ia32_Breakpoint(dbg_info *dbgi, ir_node *block, ir_node *mem);
296 
297 extern ir_op *op_ia32_Bsf;
298 
299 static inline bool is_ia32_Bsf(ir_node const *const n)
300 {
301  return get_irn_op(n) == op_ia32_Bsf;
302 }
303 
307 ir_node *new_bd_ia32_Bsf(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand);
308 
309 extern ir_op *op_ia32_Bsr;
310 
311 static inline bool is_ia32_Bsr(ir_node const *const n)
312 {
313  return get_irn_op(n) == op_ia32_Bsr;
314 }
315 
319 ir_node *new_bd_ia32_Bsr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand);
320 
321 extern ir_op *op_ia32_Bswap;
322 
323 static inline bool is_ia32_Bswap(ir_node const *const n)
324 {
325  return get_irn_op(n) == op_ia32_Bswap;
326 }
327 
331 ir_node *new_bd_ia32_Bswap(dbg_info *dbgi, ir_node *block, ir_node *val);
332 
333 extern ir_op *op_ia32_Bswap16;
334 
335 static inline bool is_ia32_Bswap16(ir_node const *const n)
336 {
337  return get_irn_op(n) == op_ia32_Bswap16;
338 }
339 
343 ir_node *new_bd_ia32_Bswap16(dbg_info *dbgi, ir_node *block, ir_node *val);
344 
345 extern ir_op *op_ia32_Bt;
346 
347 static inline bool is_ia32_Bt(ir_node const *const n)
348 {
349  return get_irn_op(n) == op_ia32_Bt;
350 }
351 
355 ir_node *new_bd_ia32_Bt(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
356 
357 extern ir_op *op_ia32_CMovcc;
358 
359 static inline bool is_ia32_CMovcc(ir_node const *const n)
360 {
361  return get_irn_op(n) == op_ia32_CMovcc;
362 }
363 
367 ir_node *new_bd_ia32_CMovcc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val_false, ir_node *val_true, ir_node *eflags, x86_condition_code_t condition_code);
368 
369 extern ir_op *op_ia32_Call;
370 
371 static inline bool is_ia32_Call(ir_node const *const n)
372 {
373  return get_irn_op(n) == op_ia32_Call;
374 }
375 
379 ir_node *new_bd_ia32_Call(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, int n_res, unsigned pop, ir_type *call_tp);
380 
381 extern ir_op *op_ia32_ChangeCW;
382 
383 static inline bool is_ia32_ChangeCW(ir_node const *const n)
384 {
385  return get_irn_op(n) == op_ia32_ChangeCW;
386 }
387 
391 ir_node *new_bd_ia32_ChangeCW(dbg_info *dbgi, ir_node *block);
392 
393 extern ir_op *op_ia32_ClimbFrame;
394 
395 static inline bool is_ia32_ClimbFrame(ir_node const *const n)
396 {
397  return get_irn_op(n) == op_ia32_ClimbFrame;
398 }
399 
403 ir_node *new_bd_ia32_ClimbFrame(dbg_info *dbgi, ir_node *block, ir_node *frame, unsigned count);
404 
405 extern ir_op *op_ia32_Cltd;
406 
407 static inline bool is_ia32_Cltd(ir_node const *const n)
408 {
409  return get_irn_op(n) == op_ia32_Cltd;
410 }
411 
415 ir_node *new_bd_ia32_Cltd(dbg_info *dbgi, ir_node *block, ir_node *val);
416 
417 extern ir_op *op_ia32_Cmc;
418 
419 static inline bool is_ia32_Cmc(ir_node const *const n)
420 {
421  return get_irn_op(n) == op_ia32_Cmc;
422 }
423 
427 ir_node *new_bd_ia32_Cmc(dbg_info *dbgi, ir_node *block, ir_node *op0);
428 
429 extern ir_op *op_ia32_Cmp;
430 
431 static inline bool is_ia32_Cmp(ir_node const *const n)
432 {
433  return get_irn_op(n) == op_ia32_Cmp;
434 }
435 
439 ir_node *new_bd_ia32_Cmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted);
443 ir_node *new_bd_ia32_Cmp_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted);
444 
445 extern ir_op *op_ia32_CmpXChgMem;
446 
447 static inline bool is_ia32_CmpXChgMem(ir_node const *const n)
448 {
449  return get_irn_op(n) == op_ia32_CmpXChgMem;
450 }
451 
455 ir_node *new_bd_ia32_CmpXChgMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *old, ir_node *new);
456 
457 extern ir_op *op_ia32_Const;
458 
459 static inline bool is_ia32_Const(ir_node const *const n)
460 {
461  return get_irn_op(n) == op_ia32_Const;
462 }
463 
467 ir_node *new_bd_ia32_Const(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm);
468 
469 extern ir_op *op_ia32_Conv_FP2FP;
470 
471 static inline bool is_ia32_Conv_FP2FP(ir_node const *const n)
472 {
473  return get_irn_op(n) == op_ia32_Conv_FP2FP;
474 }
475 
479 ir_node *new_bd_ia32_Conv_FP2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *tgt_mode);
480 
481 extern ir_op *op_ia32_Conv_FP2I;
482 
483 static inline bool is_ia32_Conv_FP2I(ir_node const *const n)
484 {
485  return get_irn_op(n) == op_ia32_Conv_FP2I;
486 }
487 
491 ir_node *new_bd_ia32_Conv_FP2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *src_mode);
492 
493 extern ir_op *op_ia32_Conv_I2FP;
494 
495 static inline bool is_ia32_Conv_I2FP(ir_node const *const n)
496 {
497  return get_irn_op(n) == op_ia32_Conv_I2FP;
498 }
499 
503 ir_node *new_bd_ia32_Conv_I2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *tgt_mode);
504 
505 extern ir_op *op_ia32_Conv_I2I;
506 
507 static inline bool is_ia32_Conv_I2I(ir_node const *const n)
508 {
509  return get_irn_op(n) == op_ia32_Conv_I2I;
510 }
511 
515 ir_node *new_bd_ia32_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *smaller_mode);
519 ir_node *new_bd_ia32_Conv_I2I_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *smaller_mode);
520 
521 extern ir_op *op_ia32_CopyB;
522 
523 static inline bool is_ia32_CopyB(ir_node const *const n)
524 {
525  return get_irn_op(n) == op_ia32_CopyB;
526 }
527 
531 ir_node *new_bd_ia32_CopyB(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *count, ir_node *mem, unsigned size);
532 
533 extern ir_op *op_ia32_CopyB_i;
534 
535 static inline bool is_ia32_CopyB_i(ir_node const *const n)
536 {
537  return get_irn_op(n) == op_ia32_CopyB_i;
538 }
539 
543 ir_node *new_bd_ia32_CopyB_i(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *mem, unsigned size);
544 
545 extern ir_op *op_ia32_CopyEbpEsp;
546 
547 static inline bool is_ia32_CopyEbpEsp(ir_node const *const n)
548 {
549  return get_irn_op(n) == op_ia32_CopyEbpEsp;
550 }
551 
555 ir_node *new_bd_ia32_CopyEbpEsp(dbg_info *dbgi, ir_node *block, ir_node *ebp);
556 
557 extern ir_op *op_ia32_CvtSI2SD;
558 
559 static inline bool is_ia32_CvtSI2SD(ir_node const *const n)
560 {
561  return get_irn_op(n) == op_ia32_CvtSI2SD;
562 }
563 
567 ir_node *new_bd_ia32_CvtSI2SD(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
568 
569 extern ir_op *op_ia32_CvtSI2SS;
570 
571 static inline bool is_ia32_CvtSI2SS(ir_node const *const n)
572 {
573  return get_irn_op(n) == op_ia32_CvtSI2SS;
574 }
575 
579 ir_node *new_bd_ia32_CvtSI2SS(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
580 
581 extern ir_op *op_ia32_Cwtl;
582 
583 static inline bool is_ia32_Cwtl(ir_node const *const n)
584 {
585  return get_irn_op(n) == op_ia32_Cwtl;
586 }
587 
591 ir_node *new_bd_ia32_Cwtl(dbg_info *dbgi, ir_node *block, ir_node *val);
592 
593 extern ir_op *op_ia32_Dec;
594 
595 static inline bool is_ia32_Dec(ir_node const *const n)
596 {
597  return get_irn_op(n) == op_ia32_Dec;
598 }
599 
603 ir_node *new_bd_ia32_Dec(dbg_info *dbgi, ir_node *block, ir_node *val);
604 
605 extern ir_op *op_ia32_DecMem;
606 
607 static inline bool is_ia32_DecMem(ir_node const *const n)
608 {
609  return get_irn_op(n) == op_ia32_DecMem;
610 }
611 
615 ir_node *new_bd_ia32_DecMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
616 
617 extern ir_op *op_ia32_Div;
618 
619 static inline bool is_ia32_Div(ir_node const *const n)
620 {
621  return get_irn_op(n) == op_ia32_Div;
622 }
623 
627 ir_node *new_bd_ia32_Div(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high);
628 
629 extern ir_op *op_ia32_Enter;
630 
631 static inline bool is_ia32_Enter(ir_node const *const n)
632 {
633  return get_irn_op(n) == op_ia32_Enter;
634 }
635 
639 ir_node *new_bd_ia32_Enter(dbg_info *dbgi, ir_node *block, ir_node *op0);
640 
641 extern ir_op *op_ia32_FldCW;
642 
643 static inline bool is_ia32_FldCW(ir_node const *const n)
644 {
645  return get_irn_op(n) == op_ia32_FldCW;
646 }
647 
651 ir_node *new_bd_ia32_FldCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
652 
653 extern ir_op *op_ia32_FnstCW;
654 
655 static inline bool is_ia32_FnstCW(ir_node const *const n)
656 {
657  return get_irn_op(n) == op_ia32_FnstCW;
658 }
659 
663 ir_node *new_bd_ia32_FnstCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *fpcw);
664 
665 extern ir_op *op_ia32_FnstCWNOP;
666 
667 static inline bool is_ia32_FnstCWNOP(ir_node const *const n)
668 {
669  return get_irn_op(n) == op_ia32_FnstCWNOP;
670 }
671 
675 ir_node *new_bd_ia32_FnstCWNOP(dbg_info *dbgi, ir_node *block, ir_node *fpcw);
676 
677 extern ir_op *op_ia32_FtstFnstsw;
678 
679 static inline bool is_ia32_FtstFnstsw(ir_node const *const n)
680 {
681  return get_irn_op(n) == op_ia32_FtstFnstsw;
682 }
683 
687 ir_node *new_bd_ia32_FtstFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, bool ins_permuted);
688 
689 extern ir_op *op_ia32_FucomFnstsw;
690 
691 static inline bool is_ia32_FucomFnstsw(ir_node const *const n)
692 {
693  return get_irn_op(n) == op_ia32_FucomFnstsw;
694 }
695 
699 ir_node *new_bd_ia32_FucomFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted);
700 
701 extern ir_op *op_ia32_Fucomi;
702 
703 static inline bool is_ia32_Fucomi(ir_node const *const n)
704 {
705  return get_irn_op(n) == op_ia32_Fucomi;
706 }
707 
711 ir_node *new_bd_ia32_Fucomi(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted);
712 
713 extern ir_op *op_ia32_FucomppFnstsw;
714 
715 static inline bool is_ia32_FucomppFnstsw(ir_node const *const n)
716 {
717  return get_irn_op(n) == op_ia32_FucomppFnstsw;
718 }
719 
723 ir_node *new_bd_ia32_FucomppFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted);
724 
725 extern ir_op *op_ia32_GetEIP;
726 
727 static inline bool is_ia32_GetEIP(ir_node const *const n)
728 {
729  return get_irn_op(n) == op_ia32_GetEIP;
730 }
731 
735 ir_node *new_bd_ia32_GetEIP(dbg_info *dbgi, ir_node *block);
736 
737 extern ir_op *op_ia32_IDiv;
738 
739 static inline bool is_ia32_IDiv(ir_node const *const n)
740 {
741  return get_irn_op(n) == op_ia32_IDiv;
742 }
743 
747 ir_node *new_bd_ia32_IDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high);
748 
749 extern ir_op *op_ia32_IJmp;
750 
751 static inline bool is_ia32_IJmp(ir_node const *const n)
752 {
753  return get_irn_op(n) == op_ia32_IJmp;
754 }
755 
759 ir_node *new_bd_ia32_IJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *target);
760 
761 extern ir_op *op_ia32_IMul;
762 
763 static inline bool is_ia32_IMul(ir_node const *const n)
764 {
765  return get_irn_op(n) == op_ia32_IMul;
766 }
767 
771 ir_node *new_bd_ia32_IMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
775 ir_node *new_bd_ia32_IMul_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
776 
777 extern ir_op *op_ia32_IMul1OP;
778 
779 static inline bool is_ia32_IMul1OP(ir_node const *const n)
780 {
781  return get_irn_op(n) == op_ia32_IMul1OP;
782 }
783 
787 ir_node *new_bd_ia32_IMul1OP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
788 
789 extern ir_op *op_ia32_IMulImm;
790 
791 static inline bool is_ia32_IMulImm(ir_node const *const n)
792 {
793  return get_irn_op(n) == op_ia32_IMulImm;
794 }
795 
799 ir_node *new_bd_ia32_IMulImm(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
803 ir_node *new_bd_ia32_IMulImm_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
804 
805 extern ir_op *op_ia32_Immediate;
806 
807 static inline bool is_ia32_Immediate(ir_node const *const n)
808 {
809  return get_irn_op(n) == op_ia32_Immediate;
810 }
811 
815 ir_node *new_bd_ia32_Immediate(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm);
816 
817 extern ir_op *op_ia32_Inc;
818 
819 static inline bool is_ia32_Inc(ir_node const *const n)
820 {
821  return get_irn_op(n) == op_ia32_Inc;
822 }
823 
827 ir_node *new_bd_ia32_Inc(dbg_info *dbgi, ir_node *block, ir_node *val);
828 
829 extern ir_op *op_ia32_IncMem;
830 
831 static inline bool is_ia32_IncMem(ir_node const *const n)
832 {
833  return get_irn_op(n) == op_ia32_IncMem;
834 }
835 
839 ir_node *new_bd_ia32_IncMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
840 
841 extern ir_op *op_ia32_Inport;
842 
843 static inline bool is_ia32_Inport(ir_node const *const n)
844 {
845  return get_irn_op(n) == op_ia32_Inport;
846 }
847 
851 ir_node *new_bd_ia32_Inport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *mem);
852 
853 extern ir_op *op_ia32_Jcc;
854 
855 static inline bool is_ia32_Jcc(ir_node const *const n)
856 {
857  return get_irn_op(n) == op_ia32_Jcc;
858 }
859 
863 ir_node *new_bd_ia32_Jcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code);
864 
865 extern ir_op *op_ia32_Jmp;
866 
867 static inline bool is_ia32_Jmp(ir_node const *const n)
868 {
869  return get_irn_op(n) == op_ia32_Jmp;
870 }
871 
875 ir_node *new_bd_ia32_Jmp(dbg_info *dbgi, ir_node *block);
876 
877 extern ir_op *op_ia32_LdTls;
878 
879 static inline bool is_ia32_LdTls(ir_node const *const n)
880 {
881  return get_irn_op(n) == op_ia32_LdTls;
882 }
883 
887 ir_node *new_bd_ia32_LdTls(dbg_info *dbgi, ir_node *block);
888 
889 extern ir_op *op_ia32_Lea;
890 
891 static inline bool is_ia32_Lea(ir_node const *const n)
892 {
893  return get_irn_op(n) == op_ia32_Lea;
894 }
895 
899 ir_node *new_bd_ia32_Lea(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index);
900 
901 extern ir_op *op_ia32_Leave;
902 
903 static inline bool is_ia32_Leave(ir_node const *const n)
904 {
905  return get_irn_op(n) == op_ia32_Leave;
906 }
907 
911 ir_node *new_bd_ia32_Leave(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1);
912 
913 extern ir_op *op_ia32_Load;
914 
915 static inline bool is_ia32_Load(ir_node const *const n)
916 {
917  return get_irn_op(n) == op_ia32_Load;
918 }
919 
923 ir_node *new_bd_ia32_Load(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
924 
925 extern ir_op *op_ia32_Minus64;
926 
927 static inline bool is_ia32_Minus64(ir_node const *const n)
928 {
929  return get_irn_op(n) == op_ia32_Minus64;
930 }
931 
935 ir_node *new_bd_ia32_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high);
936 
937 extern ir_op *op_ia32_Mul;
938 
939 static inline bool is_ia32_Mul(ir_node const *const n)
940 {
941  return get_irn_op(n) == op_ia32_Mul;
942 }
943 
947 ir_node *new_bd_ia32_Mul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
948 
949 extern ir_op *op_ia32_Neg;
950 
951 static inline bool is_ia32_Neg(ir_node const *const n)
952 {
953  return get_irn_op(n) == op_ia32_Neg;
954 }
955 
959 ir_node *new_bd_ia32_Neg(dbg_info *dbgi, ir_node *block, ir_node *val);
960 
961 extern ir_op *op_ia32_NegMem;
962 
963 static inline bool is_ia32_NegMem(ir_node const *const n)
964 {
965  return get_irn_op(n) == op_ia32_NegMem;
966 }
967 
971 ir_node *new_bd_ia32_NegMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
972 
973 extern ir_op *op_ia32_NoReg_FP;
974 
975 static inline bool is_ia32_NoReg_FP(ir_node const *const n)
976 {
977  return get_irn_op(n) == op_ia32_NoReg_FP;
978 }
979 
983 ir_node *new_bd_ia32_NoReg_FP(dbg_info *dbgi, ir_node *block);
984 
985 extern ir_op *op_ia32_NoReg_GP;
986 
987 static inline bool is_ia32_NoReg_GP(ir_node const *const n)
988 {
989  return get_irn_op(n) == op_ia32_NoReg_GP;
990 }
991 
995 ir_node *new_bd_ia32_NoReg_GP(dbg_info *dbgi, ir_node *block);
996 
997 extern ir_op *op_ia32_NoReg_XMM;
998 
999 static inline bool is_ia32_NoReg_XMM(ir_node const *const n)
1000 {
1001  return get_irn_op(n) == op_ia32_NoReg_XMM;
1002 }
1003 
1007 ir_node *new_bd_ia32_NoReg_XMM(dbg_info *dbgi, ir_node *block);
1008 
1009 extern ir_op *op_ia32_Not;
1010 
1011 static inline bool is_ia32_Not(ir_node const *const n)
1012 {
1013  return get_irn_op(n) == op_ia32_Not;
1014 }
1015 
1019 ir_node *new_bd_ia32_Not(dbg_info *dbgi, ir_node *block, ir_node *val);
1023 ir_node *new_bd_ia32_Not_8bit(dbg_info *dbgi, ir_node *block, ir_node *val);
1024 
1025 extern ir_op *op_ia32_NotMem;
1026 
1027 static inline bool is_ia32_NotMem(ir_node const *const n)
1028 {
1029  return get_irn_op(n) == op_ia32_NotMem;
1030 }
1031 
1035 ir_node *new_bd_ia32_NotMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1036 
1037 extern ir_op *op_ia32_Or;
1038 
1039 static inline bool is_ia32_Or(ir_node const *const n)
1040 {
1041  return get_irn_op(n) == op_ia32_Or;
1042 }
1043 
1047 ir_node *new_bd_ia32_Or(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
1051 ir_node *new_bd_ia32_Or_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
1052 
1053 extern ir_op *op_ia32_OrMem;
1054 
1055 static inline bool is_ia32_OrMem(ir_node const *const n)
1056 {
1057  return get_irn_op(n) == op_ia32_OrMem;
1058 }
1059 
1063 ir_node *new_bd_ia32_OrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1067 ir_node *new_bd_ia32_OrMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1068 
1069 extern ir_op *op_ia32_Outport;
1070 
1071 static inline bool is_ia32_Outport(ir_node const *const n)
1072 {
1073  return get_irn_op(n) == op_ia32_Outport;
1074 }
1075 
1079 ir_node *new_bd_ia32_Outport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *value, ir_node *mem);
1080 
1081 extern ir_op *op_ia32_Pop;
1082 
1083 static inline bool is_ia32_Pop(ir_node const *const n)
1084 {
1085  return get_irn_op(n) == op_ia32_Pop;
1086 }
1087 
1091 ir_node *new_bd_ia32_Pop(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack);
1095 ir_node *new_bd_ia32_Pop_ebp(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack);
1096 
1097 extern ir_op *op_ia32_PopMem;
1098 
1099 static inline bool is_ia32_PopMem(ir_node const *const n)
1100 {
1101  return get_irn_op(n) == op_ia32_PopMem;
1102 }
1103 
1107 ir_node *new_bd_ia32_PopMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack);
1108 
1109 extern ir_op *op_ia32_Popcnt;
1110 
1111 static inline bool is_ia32_Popcnt(ir_node const *const n)
1112 {
1113  return get_irn_op(n) == op_ia32_Popcnt;
1114 }
1115 
1119 ir_node *new_bd_ia32_Popcnt(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand);
1120 
1121 extern ir_op *op_ia32_Prefetch;
1122 
1123 static inline bool is_ia32_Prefetch(ir_node const *const n)
1124 {
1125  return get_irn_op(n) == op_ia32_Prefetch;
1126 }
1127 
1131 ir_node *new_bd_ia32_Prefetch(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1132 
1133 extern ir_op *op_ia32_Prefetch0;
1134 
1135 static inline bool is_ia32_Prefetch0(ir_node const *const n)
1136 {
1137  return get_irn_op(n) == op_ia32_Prefetch0;
1138 }
1139 
1143 ir_node *new_bd_ia32_Prefetch0(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1144 
1145 extern ir_op *op_ia32_Prefetch1;
1146 
1147 static inline bool is_ia32_Prefetch1(ir_node const *const n)
1148 {
1149  return get_irn_op(n) == op_ia32_Prefetch1;
1150 }
1151 
1155 ir_node *new_bd_ia32_Prefetch1(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1156 
1157 extern ir_op *op_ia32_Prefetch2;
1158 
1159 static inline bool is_ia32_Prefetch2(ir_node const *const n)
1160 {
1161  return get_irn_op(n) == op_ia32_Prefetch2;
1162 }
1163 
1167 ir_node *new_bd_ia32_Prefetch2(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1168 
1169 extern ir_op *op_ia32_PrefetchNTA;
1170 
1171 static inline bool is_ia32_PrefetchNTA(ir_node const *const n)
1172 {
1173  return get_irn_op(n) == op_ia32_PrefetchNTA;
1174 }
1175 
1179 ir_node *new_bd_ia32_PrefetchNTA(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1180 
1181 extern ir_op *op_ia32_PrefetchW;
1182 
1183 static inline bool is_ia32_PrefetchW(ir_node const *const n)
1184 {
1185  return get_irn_op(n) == op_ia32_PrefetchW;
1186 }
1187 
1191 ir_node *new_bd_ia32_PrefetchW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1192 
1193 extern ir_op *op_ia32_Push;
1194 
1195 static inline bool is_ia32_Push(ir_node const *const n)
1196 {
1197  return get_irn_op(n) == op_ia32_Push;
1198 }
1199 
1203 ir_node *new_bd_ia32_Push(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *stack, ir_mode *store_mode);
1204 
1205 extern ir_op *op_ia32_PushEax;
1206 
1207 static inline bool is_ia32_PushEax(ir_node const *const n)
1208 {
1209  return get_irn_op(n) == op_ia32_PushEax;
1210 }
1211 
1215 ir_node *new_bd_ia32_PushEax(dbg_info *dbgi, ir_node *block, ir_node *stack);
1216 
1217 extern ir_op *op_ia32_Return;
1218 
1219 static inline bool is_ia32_Return(ir_node const *const n)
1220 {
1221  return get_irn_op(n) == op_ia32_Return;
1222 }
1223 
1227 ir_node *new_bd_ia32_Return(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, uint16_t pop);
1228 
1229 extern ir_op *op_ia32_Rol;
1230 
1231 static inline bool is_ia32_Rol(ir_node const *const n)
1232 {
1233  return get_irn_op(n) == op_ia32_Rol;
1234 }
1235 
1239 ir_node *new_bd_ia32_Rol(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count);
1240 
1241 extern ir_op *op_ia32_RolMem;
1242 
1243 static inline bool is_ia32_RolMem(ir_node const *const n)
1244 {
1245  return get_irn_op(n) == op_ia32_RolMem;
1246 }
1247 
1251 ir_node *new_bd_ia32_RolMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count);
1252 
1253 extern ir_op *op_ia32_Ror;
1254 
1255 static inline bool is_ia32_Ror(ir_node const *const n)
1256 {
1257  return get_irn_op(n) == op_ia32_Ror;
1258 }
1259 
1263 ir_node *new_bd_ia32_Ror(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count);
1264 
1265 extern ir_op *op_ia32_RorMem;
1266 
1267 static inline bool is_ia32_RorMem(ir_node const *const n)
1268 {
1269  return get_irn_op(n) == op_ia32_RorMem;
1270 }
1271 
1275 ir_node *new_bd_ia32_RorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count);
1276 
1277 extern ir_op *op_ia32_Sahf;
1278 
1279 static inline bool is_ia32_Sahf(ir_node const *const n)
1280 {
1281  return get_irn_op(n) == op_ia32_Sahf;
1282 }
1283 
1287 ir_node *new_bd_ia32_Sahf(dbg_info *dbgi, ir_node *block, ir_node *val);
1288 
1289 extern ir_op *op_ia32_Sar;
1290 
1291 static inline bool is_ia32_Sar(ir_node const *const n)
1292 {
1293  return get_irn_op(n) == op_ia32_Sar;
1294 }
1295 
1299 ir_node *new_bd_ia32_Sar(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count);
1300 
1301 extern ir_op *op_ia32_SarMem;
1302 
1303 static inline bool is_ia32_SarMem(ir_node const *const n)
1304 {
1305  return get_irn_op(n) == op_ia32_SarMem;
1306 }
1307 
1311 ir_node *new_bd_ia32_SarMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count);
1312 
1313 extern ir_op *op_ia32_Sbb;
1314 
1315 static inline bool is_ia32_Sbb(ir_node const *const n)
1316 {
1317  return get_irn_op(n) == op_ia32_Sbb;
1318 }
1319 
1323 ir_node *new_bd_ia32_Sbb(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *eflags);
1324 
1325 extern ir_op *op_ia32_Sbb0;
1326 
1327 static inline bool is_ia32_Sbb0(ir_node const *const n)
1328 {
1329  return get_irn_op(n) == op_ia32_Sbb0;
1330 }
1331 
1335 ir_node *new_bd_ia32_Sbb0(dbg_info *dbgi, ir_node *block, ir_node *op0);
1336 
1337 extern ir_op *op_ia32_Setcc;
1338 
1339 static inline bool is_ia32_Setcc(ir_node const *const n)
1340 {
1341  return get_irn_op(n) == op_ia32_Setcc;
1342 }
1343 
1347 ir_node *new_bd_ia32_Setcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code);
1348 
1349 extern ir_op *op_ia32_SetccMem;
1350 
1351 static inline bool is_ia32_SetccMem(ir_node const *const n)
1352 {
1353  return get_irn_op(n) == op_ia32_SetccMem;
1354 }
1355 
1359 ir_node *new_bd_ia32_SetccMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *eflags, x86_condition_code_t condition_code);
1360 
1361 extern ir_op *op_ia32_Shl;
1362 
1363 static inline bool is_ia32_Shl(ir_node const *const n)
1364 {
1365  return get_irn_op(n) == op_ia32_Shl;
1366 }
1367 
1371 ir_node *new_bd_ia32_Shl(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count);
1372 
1373 extern ir_op *op_ia32_ShlD;
1374 
1375 static inline bool is_ia32_ShlD(ir_node const *const n)
1376 {
1377  return get_irn_op(n) == op_ia32_ShlD;
1378 }
1379 
1383 ir_node *new_bd_ia32_ShlD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1387 ir_node *new_bd_ia32_ShlD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1388 
1389 extern ir_op *op_ia32_ShlMem;
1390 
1391 static inline bool is_ia32_ShlMem(ir_node const *const n)
1392 {
1393  return get_irn_op(n) == op_ia32_ShlMem;
1394 }
1395 
1399 ir_node *new_bd_ia32_ShlMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count);
1400 
1401 extern ir_op *op_ia32_Shr;
1402 
1403 static inline bool is_ia32_Shr(ir_node const *const n)
1404 {
1405  return get_irn_op(n) == op_ia32_Shr;
1406 }
1407 
1411 ir_node *new_bd_ia32_Shr(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count);
1412 
1413 extern ir_op *op_ia32_ShrD;
1414 
1415 static inline bool is_ia32_ShrD(ir_node const *const n)
1416 {
1417  return get_irn_op(n) == op_ia32_ShrD;
1418 }
1419 
1423 ir_node *new_bd_ia32_ShrD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1427 ir_node *new_bd_ia32_ShrD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1428 
1429 extern ir_op *op_ia32_ShrMem;
1430 
1431 static inline bool is_ia32_ShrMem(ir_node const *const n)
1432 {
1433  return get_irn_op(n) == op_ia32_ShrMem;
1434 }
1435 
1439 ir_node *new_bd_ia32_ShrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count);
1440 
1441 extern ir_op *op_ia32_Stc;
1442 
1443 static inline bool is_ia32_Stc(ir_node const *const n)
1444 {
1445  return get_irn_op(n) == op_ia32_Stc;
1446 }
1447 
1451 ir_node *new_bd_ia32_Stc(dbg_info *dbgi, ir_node *block);
1452 
1453 extern ir_op *op_ia32_Store;
1454 
1455 static inline bool is_ia32_Store(ir_node const *const n)
1456 {
1457  return get_irn_op(n) == op_ia32_Store;
1458 }
1459 
1463 ir_node *new_bd_ia32_Store(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1467 ir_node *new_bd_ia32_Store_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1468 
1469 extern ir_op *op_ia32_Sub;
1470 
1471 static inline bool is_ia32_Sub(ir_node const *const n)
1472 {
1473  return get_irn_op(n) == op_ia32_Sub;
1474 }
1475 
1479 ir_node *new_bd_ia32_Sub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend);
1480 
1481 extern ir_op *op_ia32_SubMem;
1482 
1483 static inline bool is_ia32_SubMem(ir_node const *const n)
1484 {
1485  return get_irn_op(n) == op_ia32_SubMem;
1486 }
1487 
1491 ir_node *new_bd_ia32_SubMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1495 ir_node *new_bd_ia32_SubMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1496 
1497 extern ir_op *op_ia32_SubSP;
1498 
1499 static inline bool is_ia32_SubSP(ir_node const *const n)
1500 {
1501  return get_irn_op(n) == op_ia32_SubSP;
1502 }
1503 
1507 ir_node *new_bd_ia32_SubSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *size);
1508 
1509 extern ir_op *op_ia32_SwitchJmp;
1510 
1511 static inline bool is_ia32_SwitchJmp(ir_node const *const n)
1512 {
1513  return get_irn_op(n) == op_ia32_SwitchJmp;
1514 }
1515 
1519 ir_node *new_bd_ia32_SwitchJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, int n_res, const ir_switch_table *switch_table, const ir_entity *table_entity);
1520 
1521 extern ir_op *op_ia32_Test;
1522 
1523 static inline bool is_ia32_Test(ir_node const *const n)
1524 {
1525  return get_irn_op(n) == op_ia32_Test;
1526 }
1527 
1531 ir_node *new_bd_ia32_Test(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted);
1535 ir_node *new_bd_ia32_Test_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted);
1536 
1537 extern ir_op *op_ia32_UD2;
1538 
1539 static inline bool is_ia32_UD2(ir_node const *const n)
1540 {
1541  return get_irn_op(n) == op_ia32_UD2;
1542 }
1543 
1547 ir_node *new_bd_ia32_UD2(dbg_info *dbgi, ir_node *block, ir_node *mem);
1548 
1549 extern ir_op *op_ia32_Ucomi;
1550 
1551 static inline bool is_ia32_Ucomi(ir_node const *const n)
1552 {
1553  return get_irn_op(n) == op_ia32_Ucomi;
1554 }
1555 
1559 ir_node *new_bd_ia32_Ucomi(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted);
1560 
1561 extern ir_op *op_ia32_Unknown;
1562 
1563 static inline bool is_ia32_Unknown(ir_node const *const n)
1564 {
1565  return get_irn_op(n) == op_ia32_Unknown;
1566 }
1567 
1571 ir_node *new_bd_ia32_Unknown(dbg_info *dbgi, ir_node *block);
1572 
1573 extern ir_op *op_ia32_Xor;
1574 
1575 static inline bool is_ia32_Xor(ir_node const *const n)
1576 {
1577  return get_irn_op(n) == op_ia32_Xor;
1578 }
1579 
1583 ir_node *new_bd_ia32_Xor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
1587 ir_node *new_bd_ia32_Xor_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
1588 
1589 extern ir_op *op_ia32_Xor0;
1590 
1591 static inline bool is_ia32_Xor0(ir_node const *const n)
1592 {
1593  return get_irn_op(n) == op_ia32_Xor0;
1594 }
1595 
1599 ir_node *new_bd_ia32_Xor0(dbg_info *dbgi, ir_node *block);
1600 
1601 extern ir_op *op_ia32_XorHighLow;
1602 
1603 static inline bool is_ia32_XorHighLow(ir_node const *const n)
1604 {
1605  return get_irn_op(n) == op_ia32_XorHighLow;
1606 }
1607 
1611 ir_node *new_bd_ia32_XorHighLow(dbg_info *dbgi, ir_node *block, ir_node *value);
1612 
1613 extern ir_op *op_ia32_XorMem;
1614 
1615 static inline bool is_ia32_XorMem(ir_node const *const n)
1616 {
1617  return get_irn_op(n) == op_ia32_XorMem;
1618 }
1619 
1623 ir_node *new_bd_ia32_XorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1627 ir_node *new_bd_ia32_XorMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1628 
1629 extern ir_op *op_ia32_emms;
1630 
1631 static inline bool is_ia32_emms(ir_node const *const n)
1632 {
1633  return get_irn_op(n) == op_ia32_emms;
1634 }
1635 
1639 ir_node *new_bd_ia32_emms(dbg_info *dbgi, ir_node *block);
1640 
1641 extern ir_op *op_ia32_fabs;
1642 
1643 static inline bool is_ia32_fabs(ir_node const *const n)
1644 {
1645  return get_irn_op(n) == op_ia32_fabs;
1646 }
1647 
1651 ir_node *new_bd_ia32_fabs(dbg_info *dbgi, ir_node *block, ir_node *value);
1652 
1653 extern ir_op *op_ia32_fadd;
1654 
1655 static inline bool is_ia32_fadd(ir_node const *const n)
1656 {
1657  return get_irn_op(n) == op_ia32_fadd;
1658 }
1659 
1663 ir_node *new_bd_ia32_fadd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw);
1664 
1665 extern ir_op *op_ia32_fchs;
1666 
1667 static inline bool is_ia32_fchs(ir_node const *const n)
1668 {
1669  return get_irn_op(n) == op_ia32_fchs;
1670 }
1671 
1675 ir_node *new_bd_ia32_fchs(dbg_info *dbgi, ir_node *block, ir_node *value);
1676 
1677 extern ir_op *op_ia32_fdiv;
1678 
1679 static inline bool is_ia32_fdiv(ir_node const *const n)
1680 {
1681  return get_irn_op(n) == op_ia32_fdiv;
1682 }
1683 
1687 ir_node *new_bd_ia32_fdiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw);
1688 
1689 extern ir_op *op_ia32_fdup;
1690 
1691 static inline bool is_ia32_fdup(ir_node const *const n)
1692 {
1693  return get_irn_op(n) == op_ia32_fdup;
1694 }
1695 
1699 ir_node *new_bd_ia32_fdup(dbg_info *dbgi, ir_node *block, ir_node *val, const arch_register_t *reg);
1700 
1701 extern ir_op *op_ia32_femms;
1702 
1703 static inline bool is_ia32_femms(ir_node const *const n)
1704 {
1705  return get_irn_op(n) == op_ia32_femms;
1706 }
1707 
1711 ir_node *new_bd_ia32_femms(dbg_info *dbgi, ir_node *block);
1712 
1713 extern ir_op *op_ia32_ffreep;
1714 
1715 static inline bool is_ia32_ffreep(ir_node const *const n)
1716 {
1717  return get_irn_op(n) == op_ia32_ffreep;
1718 }
1719 
1723 ir_node *new_bd_ia32_ffreep(dbg_info *dbgi, ir_node *block, const arch_register_t *reg);
1724 
1725 extern ir_op *op_ia32_fild;
1726 
1727 static inline bool is_ia32_fild(ir_node const *const n)
1728 {
1729  return get_irn_op(n) == op_ia32_fild;
1730 }
1731 
1735 ir_node *new_bd_ia32_fild(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1736 
1737 extern ir_op *op_ia32_fist;
1738 
1739 static inline bool is_ia32_fist(ir_node const *const n)
1740 {
1741  return get_irn_op(n) == op_ia32_fist;
1742 }
1743 
1747 ir_node *new_bd_ia32_fist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw);
1748 
1749 extern ir_op *op_ia32_fistp;
1750 
1751 static inline bool is_ia32_fistp(ir_node const *const n)
1752 {
1753  return get_irn_op(n) == op_ia32_fistp;
1754 }
1755 
1759 ir_node *new_bd_ia32_fistp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw);
1760 
1761 extern ir_op *op_ia32_fisttp;
1762 
1763 static inline bool is_ia32_fisttp(ir_node const *const n)
1764 {
1765  return get_irn_op(n) == op_ia32_fisttp;
1766 }
1767 
1771 ir_node *new_bd_ia32_fisttp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
1772 
1773 extern ir_op *op_ia32_fld;
1774 
1775 static inline bool is_ia32_fld(ir_node const *const n)
1776 {
1777  return get_irn_op(n) == op_ia32_fld;
1778 }
1779 
1783 ir_node *new_bd_ia32_fld(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_mode *load_mode);
1784 
1785 extern ir_op *op_ia32_fld1;
1786 
1787 static inline bool is_ia32_fld1(ir_node const *const n)
1788 {
1789  return get_irn_op(n) == op_ia32_fld1;
1790 }
1791 
1795 ir_node *new_bd_ia32_fld1(dbg_info *dbgi, ir_node *block);
1796 
1797 extern ir_op *op_ia32_fldl2e;
1798 
1799 static inline bool is_ia32_fldl2e(ir_node const *const n)
1800 {
1801  return get_irn_op(n) == op_ia32_fldl2e;
1802 }
1803 
1807 ir_node *new_bd_ia32_fldl2e(dbg_info *dbgi, ir_node *block);
1808 
1809 extern ir_op *op_ia32_fldl2t;
1810 
1811 static inline bool is_ia32_fldl2t(ir_node const *const n)
1812 {
1813  return get_irn_op(n) == op_ia32_fldl2t;
1814 }
1815 
1819 ir_node *new_bd_ia32_fldl2t(dbg_info *dbgi, ir_node *block);
1820 
1821 extern ir_op *op_ia32_fldlg2;
1822 
1823 static inline bool is_ia32_fldlg2(ir_node const *const n)
1824 {
1825  return get_irn_op(n) == op_ia32_fldlg2;
1826 }
1827 
1831 ir_node *new_bd_ia32_fldlg2(dbg_info *dbgi, ir_node *block);
1832 
1833 extern ir_op *op_ia32_fldln2;
1834 
1835 static inline bool is_ia32_fldln2(ir_node const *const n)
1836 {
1837  return get_irn_op(n) == op_ia32_fldln2;
1838 }
1839 
1843 ir_node *new_bd_ia32_fldln2(dbg_info *dbgi, ir_node *block);
1844 
1845 extern ir_op *op_ia32_fldpi;
1846 
1847 static inline bool is_ia32_fldpi(ir_node const *const n)
1848 {
1849  return get_irn_op(n) == op_ia32_fldpi;
1850 }
1851 
1855 ir_node *new_bd_ia32_fldpi(dbg_info *dbgi, ir_node *block);
1856 
1857 extern ir_op *op_ia32_fldz;
1858 
1859 static inline bool is_ia32_fldz(ir_node const *const n)
1860 {
1861  return get_irn_op(n) == op_ia32_fldz;
1862 }
1863 
1867 ir_node *new_bd_ia32_fldz(dbg_info *dbgi, ir_node *block);
1868 
1869 extern ir_op *op_ia32_fmul;
1870 
1871 static inline bool is_ia32_fmul(ir_node const *const n)
1872 {
1873  return get_irn_op(n) == op_ia32_fmul;
1874 }
1875 
1879 ir_node *new_bd_ia32_fmul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw);
1880 
1881 extern ir_op *op_ia32_fpop;
1882 
1883 static inline bool is_ia32_fpop(ir_node const *const n)
1884 {
1885  return get_irn_op(n) == op_ia32_fpop;
1886 }
1887 
1891 ir_node *new_bd_ia32_fpop(dbg_info *dbgi, ir_node *block, const arch_register_t *reg);
1892 
1893 extern ir_op *op_ia32_fst;
1894 
1895 static inline bool is_ia32_fst(ir_node const *const n)
1896 {
1897  return get_irn_op(n) == op_ia32_fst;
1898 }
1899 
1903 ir_node *new_bd_ia32_fst(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *store_mode);
1904 
1905 extern ir_op *op_ia32_fstp;
1906 
1907 static inline bool is_ia32_fstp(ir_node const *const n)
1908 {
1909  return get_irn_op(n) == op_ia32_fstp;
1910 }
1911 
1915 ir_node *new_bd_ia32_fstp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *store_mode);
1916 
1917 extern ir_op *op_ia32_fsub;
1918 
1919 static inline bool is_ia32_fsub(ir_node const *const n)
1920 {
1921  return get_irn_op(n) == op_ia32_fsub;
1922 }
1923 
1927 ir_node *new_bd_ia32_fsub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw);
1928 
1929 extern ir_op *op_ia32_fxch;
1930 
1931 static inline bool is_ia32_fxch(ir_node const *const n)
1932 {
1933  return get_irn_op(n) == op_ia32_fxch;
1934 }
1935 
1939 ir_node *new_bd_ia32_fxch(dbg_info *dbgi, ir_node *block, const arch_register_t *reg);
1940 
1941 extern ir_op *op_ia32_l_Adc;
1942 
1943 static inline bool is_ia32_l_Adc(ir_node const *const n)
1944 {
1945  return get_irn_op(n) == op_ia32_l_Adc;
1946 }
1947 
1951 ir_node *new_bd_ia32_l_Adc(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *eflags, ir_mode *mode);
1952 
1953 extern ir_op *op_ia32_l_Add;
1954 
1955 static inline bool is_ia32_l_Add(ir_node const *const n)
1956 {
1957  return get_irn_op(n) == op_ia32_l_Add;
1958 }
1959 
1963 ir_node *new_bd_ia32_l_Add(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
1964 
1965 extern ir_op *op_ia32_l_FloattoLL;
1966 
1967 static inline bool is_ia32_l_FloattoLL(ir_node const *const n)
1968 {
1969  return get_irn_op(n) == op_ia32_l_FloattoLL;
1970 }
1971 
1975 ir_node *new_bd_ia32_l_FloattoLL(dbg_info *dbgi, ir_node *block, ir_node *val);
1976 
1977 extern ir_op *op_ia32_l_IMul;
1978 
1979 static inline bool is_ia32_l_IMul(ir_node const *const n)
1980 {
1981  return get_irn_op(n) == op_ia32_l_IMul;
1982 }
1983 
1987 ir_node *new_bd_ia32_l_IMul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
1988 
1989 extern ir_op *op_ia32_l_LLtoFloat;
1990 
1991 static inline bool is_ia32_l_LLtoFloat(ir_node const *const n)
1992 {
1993  return get_irn_op(n) == op_ia32_l_LLtoFloat;
1994 }
1995 
1999 ir_node *new_bd_ia32_l_LLtoFloat(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_mode *mode);
2000 
2001 extern ir_op *op_ia32_l_Minus64;
2002 
2003 static inline bool is_ia32_l_Minus64(ir_node const *const n)
2004 {
2005  return get_irn_op(n) == op_ia32_l_Minus64;
2006 }
2007 
2011 ir_node *new_bd_ia32_l_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high);
2012 
2013 extern ir_op *op_ia32_l_Mul;
2014 
2015 static inline bool is_ia32_l_Mul(ir_node const *const n)
2016 {
2017  return get_irn_op(n) == op_ia32_l_Mul;
2018 }
2019 
2023 ir_node *new_bd_ia32_l_Mul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
2024 
2025 extern ir_op *op_ia32_l_Sbb;
2026 
2027 static inline bool is_ia32_l_Sbb(ir_node const *const n)
2028 {
2029  return get_irn_op(n) == op_ia32_l_Sbb;
2030 }
2031 
2035 ir_node *new_bd_ia32_l_Sbb(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, ir_mode *mode);
2036 
2037 extern ir_op *op_ia32_l_Sub;
2038 
2039 static inline bool is_ia32_l_Sub(ir_node const *const n)
2040 {
2041  return get_irn_op(n) == op_ia32_l_Sub;
2042 }
2043 
2047 ir_node *new_bd_ia32_l_Sub(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend);
2048 
2049 extern ir_op *op_ia32_xAdd;
2050 
2051 static inline bool is_ia32_xAdd(ir_node const *const n)
2052 {
2053  return get_irn_op(n) == op_ia32_xAdd;
2054 }
2055 
2059 ir_node *new_bd_ia32_xAdd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2060 
2061 extern ir_op *op_ia32_xAllOnes;
2062 
2063 static inline bool is_ia32_xAllOnes(ir_node const *const n)
2064 {
2065  return get_irn_op(n) == op_ia32_xAllOnes;
2066 }
2067 
2071 ir_node *new_bd_ia32_xAllOnes(dbg_info *dbgi, ir_node *block);
2072 
2073 extern ir_op *op_ia32_xAnd;
2074 
2075 static inline bool is_ia32_xAnd(ir_node const *const n)
2076 {
2077  return get_irn_op(n) == op_ia32_xAnd;
2078 }
2079 
2083 ir_node *new_bd_ia32_xAnd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2084 
2085 extern ir_op *op_ia32_xAndNot;
2086 
2087 static inline bool is_ia32_xAndNot(ir_node const *const n)
2088 {
2089  return get_irn_op(n) == op_ia32_xAndNot;
2090 }
2091 
2095 ir_node *new_bd_ia32_xAndNot(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2096 
2097 extern ir_op *op_ia32_xDiv;
2098 
2099 static inline bool is_ia32_xDiv(ir_node const *const n)
2100 {
2101  return get_irn_op(n) == op_ia32_xDiv;
2102 }
2103 
2107 ir_node *new_bd_ia32_xDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2108 
2109 extern ir_op *op_ia32_xLoad;
2110 
2111 static inline bool is_ia32_xLoad(ir_node const *const n)
2112 {
2113  return get_irn_op(n) == op_ia32_xLoad;
2114 }
2115 
2119 ir_node *new_bd_ia32_xLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_mode *load_mode);
2120 
2121 extern ir_op *op_ia32_xMax;
2122 
2123 static inline bool is_ia32_xMax(ir_node const *const n)
2124 {
2125  return get_irn_op(n) == op_ia32_xMax;
2126 }
2127 
2131 ir_node *new_bd_ia32_xMax(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2132 
2133 extern ir_op *op_ia32_xMin;
2134 
2135 static inline bool is_ia32_xMin(ir_node const *const n)
2136 {
2137  return get_irn_op(n) == op_ia32_xMin;
2138 }
2139 
2143 ir_node *new_bd_ia32_xMin(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2144 
2145 extern ir_op *op_ia32_xMovd;
2146 
2147 static inline bool is_ia32_xMovd(ir_node const *const n)
2148 {
2149  return get_irn_op(n) == op_ia32_xMovd;
2150 }
2151 
2155 ir_node *new_bd_ia32_xMovd(dbg_info *dbgi, ir_node *block, ir_node *op0);
2156 
2157 extern ir_op *op_ia32_xMul;
2158 
2159 static inline bool is_ia32_xMul(ir_node const *const n)
2160 {
2161  return get_irn_op(n) == op_ia32_xMul;
2162 }
2163 
2167 ir_node *new_bd_ia32_xMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2168 
2169 extern ir_op *op_ia32_xOr;
2170 
2171 static inline bool is_ia32_xOr(ir_node const *const n)
2172 {
2173  return get_irn_op(n) == op_ia32_xOr;
2174 }
2175 
2179 ir_node *new_bd_ia32_xOr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2180 
2181 extern ir_op *op_ia32_xPslld;
2182 
2183 static inline bool is_ia32_xPslld(ir_node const *const n)
2184 {
2185  return get_irn_op(n) == op_ia32_xPslld;
2186 }
2187 
2191 ir_node *new_bd_ia32_xPslld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1);
2192 
2193 extern ir_op *op_ia32_xPsllq;
2194 
2195 static inline bool is_ia32_xPsllq(ir_node const *const n)
2196 {
2197  return get_irn_op(n) == op_ia32_xPsllq;
2198 }
2199 
2203 ir_node *new_bd_ia32_xPsllq(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1);
2204 
2205 extern ir_op *op_ia32_xPsrld;
2206 
2207 static inline bool is_ia32_xPsrld(ir_node const *const n)
2208 {
2209  return get_irn_op(n) == op_ia32_xPsrld;
2210 }
2211 
2215 ir_node *new_bd_ia32_xPsrld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1);
2216 
2217 extern ir_op *op_ia32_xPzero;
2218 
2219 static inline bool is_ia32_xPzero(ir_node const *const n)
2220 {
2221  return get_irn_op(n) == op_ia32_xPzero;
2222 }
2223 
2227 ir_node *new_bd_ia32_xPzero(dbg_info *dbgi, ir_node *block);
2228 
2229 extern ir_op *op_ia32_xStore;
2230 
2231 static inline bool is_ia32_xStore(ir_node const *const n)
2232 {
2233  return get_irn_op(n) == op_ia32_xStore;
2234 }
2235 
2239 ir_node *new_bd_ia32_xStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
2240 
2241 extern ir_op *op_ia32_xSub;
2242 
2243 static inline bool is_ia32_xSub(ir_node const *const n)
2244 {
2245  return get_irn_op(n) == op_ia32_xSub;
2246 }
2247 
2251 ir_node *new_bd_ia32_xSub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend);
2252 
2253 extern ir_op *op_ia32_xUnknown;
2254 
2255 static inline bool is_ia32_xUnknown(ir_node const *const n)
2256 {
2257  return get_irn_op(n) == op_ia32_xUnknown;
2258 }
2259 
2263 ir_node *new_bd_ia32_xUnknown(dbg_info *dbgi, ir_node *block);
2264 
2265 extern ir_op *op_ia32_xXor;
2266 
2267 static inline bool is_ia32_xXor(ir_node const *const n)
2268 {
2269  return get_irn_op(n) == op_ia32_xXor;
2270 }
2271 
2275 ir_node *new_bd_ia32_xXor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right);
2276 
2277 extern ir_op *op_ia32_xZero;
2278 
2279 static inline bool is_ia32_xZero(ir_node const *const n)
2280 {
2281  return get_irn_op(n) == op_ia32_xZero;
2282 }
2283 
2287 ir_node *new_bd_ia32_xZero(dbg_info *dbgi, ir_node *block);
2288 
2289 extern ir_op *op_ia32_xxLoad;
2290 
2291 static inline bool is_ia32_xxLoad(ir_node const *const n)
2292 {
2293  return get_irn_op(n) == op_ia32_xxLoad;
2294 }
2295 
2299 ir_node *new_bd_ia32_xxLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
2300 
2301 extern ir_op *op_ia32_xxStore;
2302 
2303 static inline bool is_ia32_xxStore(ir_node const *const n)
2304 {
2305  return get_irn_op(n) == op_ia32_xxStore;
2306 }
2307 
2311 ir_node *new_bd_ia32_xxStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val);
2312 
2313 
2314 typedef enum pn_ia32_Adc {
2315  pn_ia32_Adc_res = 0,
2316  pn_ia32_Adc_flags = 1,
2317  pn_ia32_Adc_M = 2,
2318 } pn_ia32_Adc;
2319 
2320 typedef enum n_ia32_Adc {
2321  n_ia32_Adc_base = 0,
2322  n_ia32_Adc_index = 1,
2323  n_ia32_Adc_mem = 2,
2324  n_ia32_Adc_left = 3,
2325  n_ia32_Adc_right = 4,
2326  n_ia32_Adc_eflags = 5,
2327 } n_ia32_Adc;
2328 
2329 typedef enum pn_ia32_Add {
2330  pn_ia32_Add_res = 0,
2331  pn_ia32_Add_flags = 1,
2332  pn_ia32_Add_M = 2,
2333 } pn_ia32_Add;
2334 
2335 typedef enum n_ia32_Add {
2336  n_ia32_Add_base = 0,
2337  n_ia32_Add_index = 1,
2338  n_ia32_Add_mem = 2,
2339  n_ia32_Add_left = 3,
2340  n_ia32_Add_right = 4,
2341 } n_ia32_Add;
2342 
2343 typedef enum pn_ia32_AddMem {
2344  pn_ia32_AddMem_unused = 0,
2345  pn_ia32_AddMem_flags = 1,
2346  pn_ia32_AddMem_M = 2,
2347 } pn_ia32_AddMem;
2348 
2349 typedef enum n_ia32_AddMem {
2350  n_ia32_AddMem_base = 0,
2351  n_ia32_AddMem_index = 1,
2352  n_ia32_AddMem_mem = 2,
2353  n_ia32_AddMem_val = 3,
2354 } n_ia32_AddMem;
2355 
2356 typedef enum pn_ia32_AddSP {
2357  pn_ia32_AddSP_stack = 0,
2358  pn_ia32_AddSP_M = 1,
2359 } pn_ia32_AddSP;
2360 
2361 typedef enum n_ia32_AddSP {
2362  n_ia32_AddSP_base = 0,
2363  n_ia32_AddSP_index = 1,
2364  n_ia32_AddSP_mem = 2,
2365  n_ia32_AddSP_stack = 3,
2366  n_ia32_AddSP_size = 4,
2367 } n_ia32_AddSP;
2368 
2369 typedef enum pn_ia32_And {
2370  pn_ia32_And_res = 0,
2371  pn_ia32_And_flags = 1,
2372  pn_ia32_And_M = 2,
2373 } pn_ia32_And;
2374 
2375 typedef enum n_ia32_And {
2376  n_ia32_And_base = 0,
2377  n_ia32_And_index = 1,
2378  n_ia32_And_mem = 2,
2379  n_ia32_And_left = 3,
2380  n_ia32_And_right = 4,
2381 } n_ia32_And;
2382 
2383 typedef enum pn_ia32_AndMem {
2384  pn_ia32_AndMem_unused = 0,
2385  pn_ia32_AndMem_flags = 1,
2386  pn_ia32_AndMem_M = 2,
2387 } pn_ia32_AndMem;
2388 
2389 typedef enum n_ia32_AndMem {
2390  n_ia32_AndMem_base = 0,
2391  n_ia32_AndMem_index = 1,
2392  n_ia32_AndMem_mem = 2,
2393  n_ia32_AndMem_val = 3,
2394 } n_ia32_AndMem;
2395 
2396 typedef enum n_ia32_Breakpoint {
2397  n_ia32_Breakpoint_mem = 0,
2398 } n_ia32_Breakpoint;
2399 
2400 typedef enum pn_ia32_Bsf {
2401  pn_ia32_Bsf_res = 0,
2402  pn_ia32_Bsf_flags = 1,
2403  pn_ia32_Bsf_M = 2,
2404 } pn_ia32_Bsf;
2405 
2406 typedef enum n_ia32_Bsf {
2407  n_ia32_Bsf_base = 0,
2408  n_ia32_Bsf_index = 1,
2409  n_ia32_Bsf_mem = 2,
2410  n_ia32_Bsf_operand = 3,
2411 } n_ia32_Bsf;
2412 
2413 typedef enum pn_ia32_Bsr {
2414  pn_ia32_Bsr_res = 0,
2415  pn_ia32_Bsr_flags = 1,
2416  pn_ia32_Bsr_M = 2,
2417 } pn_ia32_Bsr;
2418 
2419 typedef enum n_ia32_Bsr {
2420  n_ia32_Bsr_base = 0,
2421  n_ia32_Bsr_index = 1,
2422  n_ia32_Bsr_mem = 2,
2423  n_ia32_Bsr_operand = 3,
2424 } n_ia32_Bsr;
2425 
2426 typedef enum pn_ia32_Bswap {
2427  pn_ia32_Bswap_res = 0,
2428 } pn_ia32_Bswap;
2429 
2430 typedef enum n_ia32_Bswap {
2431  n_ia32_Bswap_val = 0,
2432 } n_ia32_Bswap;
2433 
2434 typedef enum pn_ia32_Bswap16 {
2435  pn_ia32_Bswap16_res = 0,
2436 } pn_ia32_Bswap16;
2437 
2438 typedef enum n_ia32_Bswap16 {
2439  n_ia32_Bswap16_val = 0,
2440 } n_ia32_Bswap16;
2441 
2442 typedef enum n_ia32_Bt {
2443  n_ia32_Bt_left = 0,
2444  n_ia32_Bt_right = 1,
2445 } n_ia32_Bt;
2446 
2447 typedef enum pn_ia32_CMovcc {
2448  pn_ia32_CMovcc_res = 0,
2449  pn_ia32_CMovcc_unused = 1,
2450  pn_ia32_CMovcc_M = 2,
2451 } pn_ia32_CMovcc;
2452 
2453 typedef enum n_ia32_CMovcc {
2454  n_ia32_CMovcc_base = 0,
2455  n_ia32_CMovcc_index = 1,
2456  n_ia32_CMovcc_mem = 2,
2457  n_ia32_CMovcc_val_false = 3,
2458  n_ia32_CMovcc_val_true = 4,
2459  n_ia32_CMovcc_eflags = 5,
2460 } n_ia32_CMovcc;
2461 
2462 typedef enum pn_ia32_Call {
2463  pn_ia32_Call_mem = 0,
2464  pn_ia32_Call_stack = 1,
2465  pn_ia32_Call_fpcw = 2,
2466  pn_ia32_Call_first_result = 3,
2467 } pn_ia32_Call;
2468 
2469 typedef enum n_ia32_Call {
2470  n_ia32_Call_base = 0,
2471  n_ia32_Call_index = 1,
2472  n_ia32_Call_mem = 2,
2473  n_ia32_Call_callee = 3,
2474  n_ia32_Call_stack = 4,
2475  n_ia32_Call_fpcw = 5,
2476  n_ia32_Call_first_argument = 6,
2477 } n_ia32_Call;
2478 
2479 typedef enum pn_ia32_ClimbFrame {
2480  pn_ia32_ClimbFrame_res = 0,
2481  pn_ia32_ClimbFrame_cnt = 1,
2482 } pn_ia32_ClimbFrame;
2483 
2484 typedef enum n_ia32_ClimbFrame {
2485  n_ia32_ClimbFrame_frame = 0,
2486 } n_ia32_ClimbFrame;
2487 
2488 typedef enum n_ia32_Cltd {
2489  n_ia32_Cltd_val = 0,
2490 } n_ia32_Cltd;
2491 
2492 typedef enum pn_ia32_Cmp {
2493  pn_ia32_Cmp_eflags = 0,
2494  pn_ia32_Cmp_unused = 1,
2495  pn_ia32_Cmp_M = 2,
2496 } pn_ia32_Cmp;
2497 
2498 typedef enum n_ia32_Cmp {
2499  n_ia32_Cmp_base = 0,
2500  n_ia32_Cmp_index = 1,
2501  n_ia32_Cmp_mem = 2,
2502  n_ia32_Cmp_left = 3,
2503  n_ia32_Cmp_right = 4,
2504 } n_ia32_Cmp;
2505 
2506 typedef enum pn_ia32_CmpXChgMem {
2507  pn_ia32_CmpXChgMem_res = 0,
2508  pn_ia32_CmpXChgMem_flags = 1,
2509  pn_ia32_CmpXChgMem_M = 2,
2510 } pn_ia32_CmpXChgMem;
2511 
2512 typedef enum n_ia32_CmpXChgMem {
2513  n_ia32_CmpXChgMem_base = 0,
2514  n_ia32_CmpXChgMem_index = 1,
2515  n_ia32_CmpXChgMem_mem = 2,
2516  n_ia32_CmpXChgMem_old = 3,
2517  n_ia32_CmpXChgMem_new = 4,
2518 } n_ia32_CmpXChgMem;
2519 
2520 typedef enum pn_ia32_Const {
2521  pn_ia32_Const_res = 0,
2522 } pn_ia32_Const;
2523 
2524 typedef enum n_ia32_Conv_FP2FP {
2525  n_ia32_Conv_FP2FP_base = 0,
2526  n_ia32_Conv_FP2FP_index = 1,
2527  n_ia32_Conv_FP2FP_mem = 2,
2528  n_ia32_Conv_FP2FP_val = 3,
2529 } n_ia32_Conv_FP2FP;
2530 
2531 typedef enum n_ia32_Conv_FP2I {
2532  n_ia32_Conv_FP2I_base = 0,
2533  n_ia32_Conv_FP2I_index = 1,
2534  n_ia32_Conv_FP2I_mem = 2,
2535  n_ia32_Conv_FP2I_val = 3,
2536 } n_ia32_Conv_FP2I;
2537 
2538 typedef enum n_ia32_Conv_I2FP {
2539  n_ia32_Conv_I2FP_base = 0,
2540  n_ia32_Conv_I2FP_index = 1,
2541  n_ia32_Conv_I2FP_mem = 2,
2542  n_ia32_Conv_I2FP_val = 3,
2543 } n_ia32_Conv_I2FP;
2544 
2545 typedef enum pn_ia32_Conv_I2I {
2546  pn_ia32_Conv_I2I_res = 0,
2547  pn_ia32_Conv_I2I_unused = 1,
2548  pn_ia32_Conv_I2I_M = 2,
2549  pn_ia32_Conv_I2I_X_regular = 3,
2550  pn_ia32_Conv_I2I_X_except = 4,
2551 } pn_ia32_Conv_I2I;
2552 
2553 typedef enum n_ia32_Conv_I2I {
2554  n_ia32_Conv_I2I_base = 0,
2555  n_ia32_Conv_I2I_index = 1,
2556  n_ia32_Conv_I2I_mem = 2,
2557  n_ia32_Conv_I2I_val = 3,
2558 } n_ia32_Conv_I2I;
2559 
2560 typedef enum pn_ia32_CopyB {
2561  pn_ia32_CopyB_dest = 0,
2562  pn_ia32_CopyB_source = 1,
2563  pn_ia32_CopyB_count = 2,
2564  pn_ia32_CopyB_M = 3,
2565 } pn_ia32_CopyB;
2566 
2567 typedef enum n_ia32_CopyB {
2568  n_ia32_CopyB_dest = 0,
2569  n_ia32_CopyB_source = 1,
2570  n_ia32_CopyB_count = 2,
2571  n_ia32_CopyB_mem = 3,
2572 } n_ia32_CopyB;
2573 
2574 typedef enum pn_ia32_CopyB_i {
2575  pn_ia32_CopyB_i_dest = 0,
2576  pn_ia32_CopyB_i_source = 1,
2577  pn_ia32_CopyB_i_M = 2,
2578 } pn_ia32_CopyB_i;
2579 
2580 typedef enum n_ia32_CopyB_i {
2581  n_ia32_CopyB_i_dest = 0,
2582  n_ia32_CopyB_i_source = 1,
2583  n_ia32_CopyB_i_mem = 2,
2584 } n_ia32_CopyB_i;
2585 
2586 typedef enum pn_ia32_CopyEbpEsp {
2587  pn_ia32_CopyEbpEsp_esp = 0,
2588 } pn_ia32_CopyEbpEsp;
2589 
2590 typedef enum n_ia32_CopyEbpEsp {
2591  n_ia32_CopyEbpEsp_ebp = 0,
2592 } n_ia32_CopyEbpEsp;
2593 
2594 typedef enum n_ia32_CvtSI2SD {
2595  n_ia32_CvtSI2SD_base = 0,
2596  n_ia32_CvtSI2SD_index = 1,
2597  n_ia32_CvtSI2SD_mem = 2,
2598  n_ia32_CvtSI2SD_val = 3,
2599 } n_ia32_CvtSI2SD;
2600 
2601 typedef enum n_ia32_CvtSI2SS {
2602  n_ia32_CvtSI2SS_base = 0,
2603  n_ia32_CvtSI2SS_index = 1,
2604  n_ia32_CvtSI2SS_mem = 2,
2605  n_ia32_CvtSI2SS_val = 3,
2606 } n_ia32_CvtSI2SS;
2607 
2608 typedef enum pn_ia32_Cwtl {
2609  pn_ia32_Cwtl_res = 0,
2610 } pn_ia32_Cwtl;
2611 
2612 typedef enum n_ia32_Cwtl {
2613  n_ia32_Cwtl_val = 0,
2614 } n_ia32_Cwtl;
2615 
2616 typedef enum pn_ia32_Dec {
2617  pn_ia32_Dec_res = 0,
2618  pn_ia32_Dec_flags = 1,
2619 } pn_ia32_Dec;
2620 
2621 typedef enum n_ia32_Dec {
2622  n_ia32_Dec_val = 0,
2623 } n_ia32_Dec;
2624 
2625 typedef enum pn_ia32_DecMem {
2626  pn_ia32_DecMem_unused = 0,
2627  pn_ia32_DecMem_flags = 1,
2628  pn_ia32_DecMem_M = 2,
2629 } pn_ia32_DecMem;
2630 
2631 typedef enum n_ia32_DecMem {
2632  n_ia32_DecMem_base = 0,
2633  n_ia32_DecMem_index = 1,
2634  n_ia32_DecMem_mem = 2,
2635 } n_ia32_DecMem;
2636 
2637 typedef enum pn_ia32_Div {
2638  pn_ia32_Div_div_res = 0,
2639  pn_ia32_Div_flags = 1,
2640  pn_ia32_Div_M = 2,
2641  pn_ia32_Div_mod_res = 3,
2642  pn_ia32_Div_X_regular = 4,
2643  pn_ia32_Div_X_except = 5,
2644 } pn_ia32_Div;
2645 
2646 typedef enum n_ia32_Div {
2647  n_ia32_Div_base = 0,
2648  n_ia32_Div_index = 1,
2649  n_ia32_Div_mem = 2,
2650  n_ia32_Div_divisor = 3,
2651  n_ia32_Div_dividend_low = 4,
2652  n_ia32_Div_dividend_high = 5,
2653 } n_ia32_Div;
2654 
2655 typedef enum pn_ia32_Enter {
2656  pn_ia32_Enter_frame = 0,
2657  pn_ia32_Enter_stack = 1,
2658  pn_ia32_Enter_M = 2,
2659 } pn_ia32_Enter;
2660 
2661 typedef enum n_ia32_FldCW {
2662  n_ia32_FldCW_base = 0,
2663  n_ia32_FldCW_index = 1,
2664  n_ia32_FldCW_mem = 2,
2665 } n_ia32_FldCW;
2666 
2667 typedef enum n_ia32_FnstCW {
2668  n_ia32_FnstCW_base = 0,
2669  n_ia32_FnstCW_index = 1,
2670  n_ia32_FnstCW_mem = 2,
2671  n_ia32_FnstCW_fpcw = 3,
2672 } n_ia32_FnstCW;
2673 
2674 typedef enum n_ia32_FnstCWNOP {
2675  n_ia32_FnstCWNOP_fpcw = 0,
2676 } n_ia32_FnstCWNOP;
2677 
2678 typedef enum pn_ia32_FtstFnstsw {
2679  pn_ia32_FtstFnstsw_flags = 0,
2680 } pn_ia32_FtstFnstsw;
2681 
2682 typedef enum n_ia32_FtstFnstsw {
2683  n_ia32_FtstFnstsw_left = 0,
2684 } n_ia32_FtstFnstsw;
2685 
2686 typedef enum pn_ia32_FucomFnstsw {
2687  pn_ia32_FucomFnstsw_flags = 0,
2688 } pn_ia32_FucomFnstsw;
2689 
2690 typedef enum n_ia32_FucomFnstsw {
2691  n_ia32_FucomFnstsw_left = 0,
2692  n_ia32_FucomFnstsw_right = 1,
2693 } n_ia32_FucomFnstsw;
2694 
2695 typedef enum pn_ia32_Fucomi {
2696  pn_ia32_Fucomi_flags = 0,
2697 } pn_ia32_Fucomi;
2698 
2699 typedef enum n_ia32_Fucomi {
2700  n_ia32_Fucomi_left = 0,
2701  n_ia32_Fucomi_right = 1,
2702 } n_ia32_Fucomi;
2703 
2704 typedef enum pn_ia32_FucomppFnstsw {
2705  pn_ia32_FucomppFnstsw_flags = 0,
2706 } pn_ia32_FucomppFnstsw;
2707 
2708 typedef enum n_ia32_FucomppFnstsw {
2709  n_ia32_FucomppFnstsw_left = 0,
2710  n_ia32_FucomppFnstsw_right = 1,
2711 } n_ia32_FucomppFnstsw;
2712 
2713 typedef enum pn_ia32_GetEIP {
2714  pn_ia32_GetEIP_res = 0,
2715 } pn_ia32_GetEIP;
2716 
2717 typedef enum pn_ia32_IDiv {
2718  pn_ia32_IDiv_div_res = 0,
2719  pn_ia32_IDiv_flags = 1,
2720  pn_ia32_IDiv_M = 2,
2721  pn_ia32_IDiv_mod_res = 3,
2722  pn_ia32_IDiv_X_regular = 4,
2723  pn_ia32_IDiv_X_except = 5,
2724 } pn_ia32_IDiv;
2725 
2726 typedef enum n_ia32_IDiv {
2727  n_ia32_IDiv_base = 0,
2728  n_ia32_IDiv_index = 1,
2729  n_ia32_IDiv_mem = 2,
2730  n_ia32_IDiv_divisor = 3,
2731  n_ia32_IDiv_dividend_low = 4,
2732  n_ia32_IDiv_dividend_high = 5,
2733 } n_ia32_IDiv;
2734 
2735 typedef enum pn_ia32_IJmp {
2736  pn_ia32_IJmp_jmp = 0,
2737  pn_ia32_IJmp_none = 1,
2738  pn_ia32_IJmp_M = 2,
2739 } pn_ia32_IJmp;
2740 
2741 typedef enum n_ia32_IJmp {
2742  n_ia32_IJmp_base = 0,
2743  n_ia32_IJmp_index = 1,
2744  n_ia32_IJmp_mem = 2,
2745  n_ia32_IJmp_target = 3,
2746 } n_ia32_IJmp;
2747 
2748 typedef enum pn_ia32_IMul {
2749  pn_ia32_IMul_res = 0,
2750  pn_ia32_IMul_flags = 1,
2751  pn_ia32_IMul_M = 2,
2752 } pn_ia32_IMul;
2753 
2754 typedef enum n_ia32_IMul {
2755  n_ia32_IMul_base = 0,
2756  n_ia32_IMul_index = 1,
2757  n_ia32_IMul_mem = 2,
2758  n_ia32_IMul_left = 3,
2759  n_ia32_IMul_right = 4,
2760 } n_ia32_IMul;
2761 
2762 typedef enum pn_ia32_IMul1OP {
2763  pn_ia32_IMul1OP_res_low = 0,
2764  pn_ia32_IMul1OP_flags = 1,
2765  pn_ia32_IMul1OP_M = 2,
2766  pn_ia32_IMul1OP_res_high = 3,
2767 } pn_ia32_IMul1OP;
2768 
2769 typedef enum n_ia32_IMul1OP {
2770  n_ia32_IMul1OP_base = 0,
2771  n_ia32_IMul1OP_index = 1,
2772  n_ia32_IMul1OP_mem = 2,
2773  n_ia32_IMul1OP_left = 3,
2774  n_ia32_IMul1OP_right = 4,
2775 } n_ia32_IMul1OP;
2776 
2777 typedef enum pn_ia32_IMulImm {
2778  pn_ia32_IMulImm_res = 0,
2779  pn_ia32_IMulImm_flags = 1,
2780  pn_ia32_IMulImm_M = 2,
2781 } pn_ia32_IMulImm;
2782 
2783 typedef enum n_ia32_IMulImm {
2784  n_ia32_IMulImm_base = 0,
2785  n_ia32_IMulImm_index = 1,
2786  n_ia32_IMulImm_mem = 2,
2787  n_ia32_IMulImm_left = 3,
2788  n_ia32_IMulImm_right = 4,
2789 } n_ia32_IMulImm;
2790 
2791 typedef enum pn_ia32_Inc {
2792  pn_ia32_Inc_res = 0,
2793  pn_ia32_Inc_flags = 1,
2794 } pn_ia32_Inc;
2795 
2796 typedef enum n_ia32_Inc {
2797  n_ia32_Inc_val = 0,
2798 } n_ia32_Inc;
2799 
2800 typedef enum pn_ia32_IncMem {
2801  pn_ia32_IncMem_unused = 0,
2802  pn_ia32_IncMem_flags = 1,
2803  pn_ia32_IncMem_M = 2,
2804 } pn_ia32_IncMem;
2805 
2806 typedef enum n_ia32_IncMem {
2807  n_ia32_IncMem_base = 0,
2808  n_ia32_IncMem_index = 1,
2809  n_ia32_IncMem_mem = 2,
2810 } n_ia32_IncMem;
2811 
2812 typedef enum pn_ia32_Inport {
2813  pn_ia32_Inport_res = 0,
2814  pn_ia32_Inport_M = 1,
2815 } pn_ia32_Inport;
2816 
2817 typedef enum n_ia32_Inport {
2818  n_ia32_Inport_port = 0,
2819  n_ia32_Inport_mem = 1,
2820 } n_ia32_Inport;
2821 
2822 typedef enum pn_ia32_Jcc {
2823  pn_ia32_Jcc_false = 0,
2824  pn_ia32_Jcc_true = 1,
2825 } pn_ia32_Jcc;
2826 
2827 typedef enum n_ia32_Jcc {
2828  n_ia32_Jcc_eflags = 0,
2829 } n_ia32_Jcc;
2830 
2831 typedef enum pn_ia32_LdTls {
2832  pn_ia32_LdTls_res = 0,
2833 } pn_ia32_LdTls;
2834 
2835 typedef enum pn_ia32_Lea {
2836  pn_ia32_Lea_res = 0,
2837 } pn_ia32_Lea;
2838 
2839 typedef enum n_ia32_Lea {
2840  n_ia32_Lea_base = 0,
2841  n_ia32_Lea_index = 1,
2842 } n_ia32_Lea;
2843 
2844 typedef enum pn_ia32_Leave {
2845  pn_ia32_Leave_frame = 0,
2846  pn_ia32_Leave_M = 1,
2847  pn_ia32_Leave_stack = 2,
2848 } pn_ia32_Leave;
2849 
2850 typedef enum pn_ia32_Load {
2851  pn_ia32_Load_res = 0,
2852  pn_ia32_Load_unused = 1,
2853  pn_ia32_Load_M = 2,
2854  pn_ia32_Load_X_regular = 3,
2855  pn_ia32_Load_X_except = 4,
2856 } pn_ia32_Load;
2857 
2858 typedef enum n_ia32_Load {
2859  n_ia32_Load_base = 0,
2860  n_ia32_Load_index = 1,
2861  n_ia32_Load_mem = 2,
2862 } n_ia32_Load;
2863 
2864 typedef enum pn_ia32_Minus64 {
2865  pn_ia32_Minus64_res_low = 0,
2866  pn_ia32_Minus64_res_high = 1,
2867 } pn_ia32_Minus64;
2868 
2869 typedef enum n_ia32_Minus64 {
2870  n_ia32_Minus64_low = 0,
2871  n_ia32_Minus64_high = 1,
2872 } n_ia32_Minus64;
2873 
2874 typedef enum pn_ia32_Mul {
2875  pn_ia32_Mul_res_low = 0,
2876  pn_ia32_Mul_flags = 1,
2877  pn_ia32_Mul_M = 2,
2878  pn_ia32_Mul_res_high = 3,
2879 } pn_ia32_Mul;
2880 
2881 typedef enum n_ia32_Mul {
2882  n_ia32_Mul_base = 0,
2883  n_ia32_Mul_index = 1,
2884  n_ia32_Mul_mem = 2,
2885  n_ia32_Mul_left = 3,
2886  n_ia32_Mul_right = 4,
2887 } n_ia32_Mul;
2888 
2889 typedef enum pn_ia32_Neg {
2890  pn_ia32_Neg_res = 0,
2891  pn_ia32_Neg_flags = 1,
2892 } pn_ia32_Neg;
2893 
2894 typedef enum n_ia32_Neg {
2895  n_ia32_Neg_val = 0,
2896 } n_ia32_Neg;
2897 
2898 typedef enum pn_ia32_NegMem {
2899  pn_ia32_NegMem_unused = 0,
2900  pn_ia32_NegMem_flags = 1,
2901  pn_ia32_NegMem_M = 2,
2902 } pn_ia32_NegMem;
2903 
2904 typedef enum n_ia32_NegMem {
2905  n_ia32_NegMem_base = 0,
2906  n_ia32_NegMem_index = 1,
2907  n_ia32_NegMem_mem = 2,
2908 } n_ia32_NegMem;
2909 
2910 typedef enum pn_ia32_Not {
2911  pn_ia32_Not_res = 0,
2912 } pn_ia32_Not;
2913 
2914 typedef enum n_ia32_Not {
2915  n_ia32_Not_val = 0,
2916 } n_ia32_Not;
2917 
2918 typedef enum pn_ia32_NotMem {
2919  pn_ia32_NotMem_unused0 = 0,
2920  pn_ia32_NotMem_unused1 = 1,
2921  pn_ia32_NotMem_M = 2,
2922 } pn_ia32_NotMem;
2923 
2924 typedef enum n_ia32_NotMem {
2925  n_ia32_NotMem_base = 0,
2926  n_ia32_NotMem_index = 1,
2927  n_ia32_NotMem_mem = 2,
2928 } n_ia32_NotMem;
2929 
2930 typedef enum pn_ia32_Or {
2931  pn_ia32_Or_res = 0,
2932  pn_ia32_Or_flags = 1,
2933  pn_ia32_Or_M = 2,
2934 } pn_ia32_Or;
2935 
2936 typedef enum n_ia32_Or {
2937  n_ia32_Or_base = 0,
2938  n_ia32_Or_index = 1,
2939  n_ia32_Or_mem = 2,
2940  n_ia32_Or_left = 3,
2941  n_ia32_Or_right = 4,
2942 } n_ia32_Or;
2943 
2944 typedef enum pn_ia32_OrMem {
2945  pn_ia32_OrMem_unused = 0,
2946  pn_ia32_OrMem_flags = 1,
2947  pn_ia32_OrMem_M = 2,
2948 } pn_ia32_OrMem;
2949 
2950 typedef enum n_ia32_OrMem {
2951  n_ia32_OrMem_base = 0,
2952  n_ia32_OrMem_index = 1,
2953  n_ia32_OrMem_mem = 2,
2954  n_ia32_OrMem_val = 3,
2955 } n_ia32_OrMem;
2956 
2957 typedef enum n_ia32_Outport {
2958  n_ia32_Outport_port = 0,
2959  n_ia32_Outport_value = 1,
2960  n_ia32_Outport_mem = 2,
2961 } n_ia32_Outport;
2962 
2963 typedef enum pn_ia32_Pop {
2964  pn_ia32_Pop_res = 0,
2965  pn_ia32_Pop_unused = 1,
2966  pn_ia32_Pop_M = 2,
2967  pn_ia32_Pop_stack = 3,
2968 } pn_ia32_Pop;
2969 
2970 typedef enum n_ia32_Pop {
2971  n_ia32_Pop_mem = 0,
2972  n_ia32_Pop_stack = 1,
2973 } n_ia32_Pop;
2974 
2975 typedef enum pn_ia32_PopMem {
2976  pn_ia32_PopMem_unused0 = 0,
2977  pn_ia32_PopMem_unused1 = 1,
2978  pn_ia32_PopMem_M = 2,
2979  pn_ia32_PopMem_stack = 3,
2980 } pn_ia32_PopMem;
2981 
2982 typedef enum n_ia32_PopMem {
2983  n_ia32_PopMem_base = 0,
2984  n_ia32_PopMem_index = 1,
2985  n_ia32_PopMem_mem = 2,
2986  n_ia32_PopMem_stack = 3,
2987 } n_ia32_PopMem;
2988 
2989 typedef enum pn_ia32_Popcnt {
2990  pn_ia32_Popcnt_res = 0,
2991  pn_ia32_Popcnt_flags = 1,
2992  pn_ia32_Popcnt_M = 2,
2993 } pn_ia32_Popcnt;
2994 
2995 typedef enum n_ia32_Popcnt {
2996  n_ia32_Popcnt_base = 0,
2997  n_ia32_Popcnt_index = 1,
2998  n_ia32_Popcnt_mem = 2,
2999  n_ia32_Popcnt_operand = 3,
3000 } n_ia32_Popcnt;
3001 
3002 typedef enum pn_ia32_Prefetch {
3003  pn_ia32_Prefetch_M = 0,
3004 } pn_ia32_Prefetch;
3005 
3006 typedef enum n_ia32_Prefetch {
3007  n_ia32_Prefetch_base = 0,
3008  n_ia32_Prefetch_index = 1,
3009  n_ia32_Prefetch_mem = 2,
3010 } n_ia32_Prefetch;
3011 
3012 typedef enum pn_ia32_Prefetch0 {
3013  pn_ia32_Prefetch0_M = 0,
3014 } pn_ia32_Prefetch0;
3015 
3016 typedef enum n_ia32_Prefetch0 {
3017  n_ia32_Prefetch0_base = 0,
3018  n_ia32_Prefetch0_index = 1,
3019  n_ia32_Prefetch0_mem = 2,
3020 } n_ia32_Prefetch0;
3021 
3022 typedef enum pn_ia32_Prefetch1 {
3023  pn_ia32_Prefetch1_M = 0,
3024 } pn_ia32_Prefetch1;
3025 
3026 typedef enum n_ia32_Prefetch1 {
3027  n_ia32_Prefetch1_base = 0,
3028  n_ia32_Prefetch1_index = 1,
3029  n_ia32_Prefetch1_mem = 2,
3030 } n_ia32_Prefetch1;
3031 
3032 typedef enum pn_ia32_Prefetch2 {
3033  pn_ia32_Prefetch2_M = 0,
3034 } pn_ia32_Prefetch2;
3035 
3036 typedef enum n_ia32_Prefetch2 {
3037  n_ia32_Prefetch2_base = 0,
3038  n_ia32_Prefetch2_index = 1,
3039  n_ia32_Prefetch2_mem = 2,
3040 } n_ia32_Prefetch2;
3041 
3042 typedef enum pn_ia32_PrefetchNTA {
3043  pn_ia32_PrefetchNTA_M = 0,
3044 } pn_ia32_PrefetchNTA;
3045 
3046 typedef enum n_ia32_PrefetchNTA {
3047  n_ia32_PrefetchNTA_base = 0,
3048  n_ia32_PrefetchNTA_index = 1,
3049  n_ia32_PrefetchNTA_mem = 2,
3050 } n_ia32_PrefetchNTA;
3051 
3052 typedef enum pn_ia32_PrefetchW {
3053  pn_ia32_PrefetchW_M = 0,
3054 } pn_ia32_PrefetchW;
3055 
3056 typedef enum n_ia32_PrefetchW {
3057  n_ia32_PrefetchW_base = 0,
3058  n_ia32_PrefetchW_index = 1,
3059  n_ia32_PrefetchW_mem = 2,
3060 } n_ia32_PrefetchW;
3061 
3062 typedef enum pn_ia32_Push {
3063  pn_ia32_Push_M = 0,
3064  pn_ia32_Push_stack = 1,
3065 } pn_ia32_Push;
3066 
3067 typedef enum n_ia32_Push {
3068  n_ia32_Push_base = 0,
3069  n_ia32_Push_index = 1,
3070  n_ia32_Push_mem = 2,
3071  n_ia32_Push_val = 3,
3072  n_ia32_Push_stack = 4,
3073 } n_ia32_Push;
3074 
3075 typedef enum pn_ia32_PushEax {
3076  pn_ia32_PushEax_stack = 0,
3077 } pn_ia32_PushEax;
3078 
3079 typedef enum n_ia32_PushEax {
3080  n_ia32_PushEax_stack = 0,
3081 } n_ia32_PushEax;
3082 
3083 typedef enum n_ia32_Return {
3084  n_ia32_Return_mem = 0,
3085  n_ia32_Return_stack = 1,
3086  n_ia32_Return_first_result = 2,
3087 } n_ia32_Return;
3088 
3089 typedef enum pn_ia32_Rol {
3090  pn_ia32_Rol_res = 0,
3091  pn_ia32_Rol_flags = 1,
3092 } pn_ia32_Rol;
3093 
3094 typedef enum n_ia32_Rol {
3095  n_ia32_Rol_val = 0,
3096  n_ia32_Rol_count = 1,
3097 } n_ia32_Rol;
3098 
3099 typedef enum pn_ia32_RolMem {
3100  pn_ia32_RolMem_unused = 0,
3101  pn_ia32_RolMem_flags = 1,
3102  pn_ia32_RolMem_M = 2,
3103 } pn_ia32_RolMem;
3104 
3105 typedef enum n_ia32_RolMem {
3106  n_ia32_RolMem_base = 0,
3107  n_ia32_RolMem_index = 1,
3108  n_ia32_RolMem_mem = 2,
3109  n_ia32_RolMem_count = 3,
3110 } n_ia32_RolMem;
3111 
3112 typedef enum pn_ia32_Ror {
3113  pn_ia32_Ror_res = 0,
3114  pn_ia32_Ror_flags = 1,
3115 } pn_ia32_Ror;
3116 
3117 typedef enum n_ia32_Ror {
3118  n_ia32_Ror_val = 0,
3119  n_ia32_Ror_count = 1,
3120 } n_ia32_Ror;
3121 
3122 typedef enum pn_ia32_RorMem {
3123  pn_ia32_RorMem_unused = 0,
3124  pn_ia32_RorMem_flags = 1,
3125  pn_ia32_RorMem_M = 2,
3126 } pn_ia32_RorMem;
3127 
3128 typedef enum n_ia32_RorMem {
3129  n_ia32_RorMem_base = 0,
3130  n_ia32_RorMem_index = 1,
3131  n_ia32_RorMem_mem = 2,
3132  n_ia32_RorMem_count = 3,
3133 } n_ia32_RorMem;
3134 
3135 typedef enum pn_ia32_Sahf {
3136  pn_ia32_Sahf_flags = 0,
3137 } pn_ia32_Sahf;
3138 
3139 typedef enum n_ia32_Sahf {
3140  n_ia32_Sahf_val = 0,
3141 } n_ia32_Sahf;
3142 
3143 typedef enum pn_ia32_Sar {
3144  pn_ia32_Sar_res = 0,
3145  pn_ia32_Sar_flags = 1,
3146 } pn_ia32_Sar;
3147 
3148 typedef enum n_ia32_Sar {
3149  n_ia32_Sar_val = 0,
3150  n_ia32_Sar_count = 1,
3151 } n_ia32_Sar;
3152 
3153 typedef enum pn_ia32_SarMem {
3154  pn_ia32_SarMem_unused = 0,
3155  pn_ia32_SarMem_flags = 1,
3156  pn_ia32_SarMem_M = 2,
3157 } pn_ia32_SarMem;
3158 
3159 typedef enum n_ia32_SarMem {
3160  n_ia32_SarMem_base = 0,
3161  n_ia32_SarMem_index = 1,
3162  n_ia32_SarMem_mem = 2,
3163  n_ia32_SarMem_count = 3,
3164 } n_ia32_SarMem;
3165 
3166 typedef enum pn_ia32_Sbb {
3167  pn_ia32_Sbb_res = 0,
3168  pn_ia32_Sbb_flags = 1,
3169  pn_ia32_Sbb_M = 2,
3170 } pn_ia32_Sbb;
3171 
3172 typedef enum n_ia32_Sbb {
3173  n_ia32_Sbb_base = 0,
3174  n_ia32_Sbb_index = 1,
3175  n_ia32_Sbb_mem = 2,
3176  n_ia32_Sbb_minuend = 3,
3177  n_ia32_Sbb_subtrahend = 4,
3178  n_ia32_Sbb_eflags = 5,
3179 } n_ia32_Sbb;
3180 
3181 typedef enum pn_ia32_Sbb0 {
3182  pn_ia32_Sbb0_res = 0,
3183  pn_ia32_Sbb0_flags = 1,
3184 } pn_ia32_Sbb0;
3185 
3186 typedef enum pn_ia32_Setcc {
3187  pn_ia32_Setcc_res = 0,
3188 } pn_ia32_Setcc;
3189 
3190 typedef enum n_ia32_Setcc {
3191  n_ia32_Setcc_eflags = 0,
3192 } n_ia32_Setcc;
3193 
3194 typedef enum n_ia32_SetccMem {
3195  n_ia32_SetccMem_base = 0,
3196  n_ia32_SetccMem_index = 1,
3197  n_ia32_SetccMem_mem = 2,
3198  n_ia32_SetccMem_eflags = 3,
3199 } n_ia32_SetccMem;
3200 
3201 typedef enum pn_ia32_Shl {
3202  pn_ia32_Shl_res = 0,
3203  pn_ia32_Shl_flags = 1,
3204 } pn_ia32_Shl;
3205 
3206 typedef enum n_ia32_Shl {
3207  n_ia32_Shl_val = 0,
3208  n_ia32_Shl_count = 1,
3209 } n_ia32_Shl;
3210 
3211 typedef enum pn_ia32_ShlD {
3212  pn_ia32_ShlD_res = 0,
3213  pn_ia32_ShlD_flags = 1,
3214 } pn_ia32_ShlD;
3215 
3216 typedef enum n_ia32_ShlD {
3217  n_ia32_ShlD_val_high = 0,
3218  n_ia32_ShlD_val_low = 1,
3219  n_ia32_ShlD_count = 2,
3220 } n_ia32_ShlD;
3221 
3222 typedef enum pn_ia32_ShlMem {
3223  pn_ia32_ShlMem_unused = 0,
3224  pn_ia32_ShlMem_flags = 1,
3225  pn_ia32_ShlMem_M = 2,
3226 } pn_ia32_ShlMem;
3227 
3228 typedef enum n_ia32_ShlMem {
3229  n_ia32_ShlMem_base = 0,
3230  n_ia32_ShlMem_index = 1,
3231  n_ia32_ShlMem_mem = 2,
3232  n_ia32_ShlMem_count = 3,
3233 } n_ia32_ShlMem;
3234 
3235 typedef enum pn_ia32_Shr {
3236  pn_ia32_Shr_res = 0,
3237  pn_ia32_Shr_flags = 1,
3238 } pn_ia32_Shr;
3239 
3240 typedef enum n_ia32_Shr {
3241  n_ia32_Shr_val = 0,
3242  n_ia32_Shr_count = 1,
3243 } n_ia32_Shr;
3244 
3245 typedef enum pn_ia32_ShrD {
3246  pn_ia32_ShrD_res = 0,
3247  pn_ia32_ShrD_flags = 1,
3248 } pn_ia32_ShrD;
3249 
3250 typedef enum n_ia32_ShrD {
3251  n_ia32_ShrD_val_high = 0,
3252  n_ia32_ShrD_val_low = 1,
3253  n_ia32_ShrD_count = 2,
3254 } n_ia32_ShrD;
3255 
3256 typedef enum pn_ia32_ShrMem {
3257  pn_ia32_ShrMem_unused = 0,
3258  pn_ia32_ShrMem_flags = 1,
3259  pn_ia32_ShrMem_M = 2,
3260 } pn_ia32_ShrMem;
3261 
3262 typedef enum n_ia32_ShrMem {
3263  n_ia32_ShrMem_base = 0,
3264  n_ia32_ShrMem_index = 1,
3265  n_ia32_ShrMem_mem = 2,
3266  n_ia32_ShrMem_count = 3,
3267 } n_ia32_ShrMem;
3268 
3269 typedef enum pn_ia32_Store {
3270  pn_ia32_Store_M = 0,
3271  pn_ia32_Store_X_regular = 1,
3272  pn_ia32_Store_X_except = 2,
3273 } pn_ia32_Store;
3274 
3275 typedef enum n_ia32_Store {
3276  n_ia32_Store_base = 0,
3277  n_ia32_Store_index = 1,
3278  n_ia32_Store_mem = 2,
3279  n_ia32_Store_val = 3,
3280 } n_ia32_Store;
3281 
3282 typedef enum pn_ia32_Sub {
3283  pn_ia32_Sub_res = 0,
3284  pn_ia32_Sub_flags = 1,
3285  pn_ia32_Sub_M = 2,
3286 } pn_ia32_Sub;
3287 
3288 typedef enum n_ia32_Sub {
3289  n_ia32_Sub_base = 0,
3290  n_ia32_Sub_index = 1,
3291  n_ia32_Sub_mem = 2,
3292  n_ia32_Sub_minuend = 3,
3293  n_ia32_Sub_subtrahend = 4,
3294 } n_ia32_Sub;
3295 
3296 typedef enum pn_ia32_SubMem {
3297  pn_ia32_SubMem_unused = 0,
3298  pn_ia32_SubMem_flags = 1,
3299  pn_ia32_SubMem_M = 2,
3300 } pn_ia32_SubMem;
3301 
3302 typedef enum n_ia32_SubMem {
3303  n_ia32_SubMem_base = 0,
3304  n_ia32_SubMem_index = 1,
3305  n_ia32_SubMem_mem = 2,
3306  n_ia32_SubMem_val = 3,
3307 } n_ia32_SubMem;
3308 
3309 typedef enum pn_ia32_SubSP {
3310  pn_ia32_SubSP_stack = 0,
3311  pn_ia32_SubSP_addr = 1,
3312  pn_ia32_SubSP_M = 2,
3313 } pn_ia32_SubSP;
3314 
3315 typedef enum n_ia32_SubSP {
3316  n_ia32_SubSP_base = 0,
3317  n_ia32_SubSP_index = 1,
3318  n_ia32_SubSP_mem = 2,
3319  n_ia32_SubSP_stack = 3,
3320  n_ia32_SubSP_size = 4,
3321 } n_ia32_SubSP;
3322 
3323 typedef enum n_ia32_SwitchJmp {
3324  n_ia32_SwitchJmp_base = 0,
3325  n_ia32_SwitchJmp_index = 1,
3326 } n_ia32_SwitchJmp;
3327 
3328 typedef enum pn_ia32_Test {
3329  pn_ia32_Test_eflags = 0,
3330  pn_ia32_Test_unused = 1,
3331  pn_ia32_Test_M = 2,
3332 } pn_ia32_Test;
3333 
3334 typedef enum n_ia32_Test {
3335  n_ia32_Test_base = 0,
3336  n_ia32_Test_index = 1,
3337  n_ia32_Test_mem = 2,
3338  n_ia32_Test_left = 3,
3339  n_ia32_Test_right = 4,
3340 } n_ia32_Test;
3341 
3342 typedef enum n_ia32_UD2 {
3343  n_ia32_UD2_mem = 0,
3344 } n_ia32_UD2;
3345 
3346 typedef enum pn_ia32_Ucomi {
3347  pn_ia32_Ucomi_flags = 0,
3348 } pn_ia32_Ucomi;
3349 
3350 typedef enum n_ia32_Ucomi {
3351  n_ia32_Ucomi_base = 0,
3352  n_ia32_Ucomi_index = 1,
3353  n_ia32_Ucomi_mem = 2,
3354  n_ia32_Ucomi_left = 3,
3355  n_ia32_Ucomi_right = 4,
3356 } n_ia32_Ucomi;
3357 
3358 typedef enum pn_ia32_Unknown {
3359  pn_ia32_Unknown_res = 0,
3360 } pn_ia32_Unknown;
3361 
3362 typedef enum pn_ia32_Xor {
3363  pn_ia32_Xor_res = 0,
3364  pn_ia32_Xor_flags = 1,
3365  pn_ia32_Xor_M = 2,
3366 } pn_ia32_Xor;
3367 
3368 typedef enum n_ia32_Xor {
3369  n_ia32_Xor_base = 0,
3370  n_ia32_Xor_index = 1,
3371  n_ia32_Xor_mem = 2,
3372  n_ia32_Xor_left = 3,
3373  n_ia32_Xor_right = 4,
3374 } n_ia32_Xor;
3375 
3376 typedef enum pn_ia32_Xor0 {
3377  pn_ia32_Xor0_res = 0,
3378  pn_ia32_Xor0_flags = 1,
3379 } pn_ia32_Xor0;
3380 
3381 typedef enum pn_ia32_XorHighLow {
3382  pn_ia32_XorHighLow_res = 0,
3383  pn_ia32_XorHighLow_flags = 1,
3384 } pn_ia32_XorHighLow;
3385 
3386 typedef enum n_ia32_XorHighLow {
3387  n_ia32_XorHighLow_value = 0,
3388 } n_ia32_XorHighLow;
3389 
3390 typedef enum pn_ia32_XorMem {
3391  pn_ia32_XorMem_unused = 0,
3392  pn_ia32_XorMem_flags = 1,
3393  pn_ia32_XorMem_M = 2,
3394 } pn_ia32_XorMem;
3395 
3396 typedef enum n_ia32_XorMem {
3397  n_ia32_XorMem_base = 0,
3398  n_ia32_XorMem_index = 1,
3399  n_ia32_XorMem_mem = 2,
3400  n_ia32_XorMem_val = 3,
3401 } n_ia32_XorMem;
3402 
3403 typedef enum n_ia32_fabs {
3404  n_ia32_fabs_value = 0,
3405 } n_ia32_fabs;
3406 
3407 typedef enum pn_ia32_fadd {
3408  pn_ia32_fadd_res = 0,
3409  pn_ia32_fadd_dummy = 1,
3410  pn_ia32_fadd_M = 2,
3411 } pn_ia32_fadd;
3412 
3413 typedef enum n_ia32_fadd {
3414  n_ia32_fadd_base = 0,
3415  n_ia32_fadd_index = 1,
3416  n_ia32_fadd_mem = 2,
3417  n_ia32_fadd_left = 3,
3418  n_ia32_fadd_right = 4,
3419  n_ia32_fadd_fpcw = 5,
3420 } n_ia32_fadd;
3421 
3422 typedef enum n_ia32_fchs {
3423  n_ia32_fchs_value = 0,
3424 } n_ia32_fchs;
3425 
3426 typedef enum pn_ia32_fdiv {
3427  pn_ia32_fdiv_res = 0,
3428  pn_ia32_fdiv_dummy = 1,
3429  pn_ia32_fdiv_M = 2,
3430 } pn_ia32_fdiv;
3431 
3432 typedef enum n_ia32_fdiv {
3433  n_ia32_fdiv_base = 0,
3434  n_ia32_fdiv_index = 1,
3435  n_ia32_fdiv_mem = 2,
3436  n_ia32_fdiv_left = 3,
3437  n_ia32_fdiv_right = 4,
3438  n_ia32_fdiv_fpcw = 5,
3439 } n_ia32_fdiv;
3440 
3441 typedef enum n_ia32_fdup {
3442  n_ia32_fdup_val = 0,
3443 } n_ia32_fdup;
3444 
3445 typedef enum pn_ia32_fild {
3446  pn_ia32_fild_res = 0,
3447  pn_ia32_fild_unused = 1,
3448  pn_ia32_fild_M = 2,
3449 } pn_ia32_fild;
3450 
3451 typedef enum n_ia32_fild {
3452  n_ia32_fild_base = 0,
3453  n_ia32_fild_index = 1,
3454  n_ia32_fild_mem = 2,
3455 } n_ia32_fild;
3456 
3457 typedef enum pn_ia32_fist {
3458  pn_ia32_fist_M = 0,
3459  pn_ia32_fist_X_regular = 1,
3460  pn_ia32_fist_X_except = 2,
3461 } pn_ia32_fist;
3462 
3463 typedef enum n_ia32_fist {
3464  n_ia32_fist_base = 0,
3465  n_ia32_fist_index = 1,
3466  n_ia32_fist_mem = 2,
3467  n_ia32_fist_val = 3,
3468  n_ia32_fist_fpcw = 4,
3469 } n_ia32_fist;
3470 
3471 typedef enum pn_ia32_fistp {
3472  pn_ia32_fistp_M = 0,
3473  pn_ia32_fistp_X_regular = 1,
3474  pn_ia32_fistp_X_except = 2,
3475 } pn_ia32_fistp;
3476 
3477 typedef enum n_ia32_fistp {
3478  n_ia32_fistp_base = 0,
3479  n_ia32_fistp_index = 1,
3480  n_ia32_fistp_mem = 2,
3481  n_ia32_fistp_val = 3,
3482  n_ia32_fistp_fpcw = 4,
3483 } n_ia32_fistp;
3484 
3485 typedef enum pn_ia32_fisttp {
3486  pn_ia32_fisttp_M = 0,
3487  pn_ia32_fisttp_X_regular = 1,
3488  pn_ia32_fisttp_X_except = 2,
3489 } pn_ia32_fisttp;
3490 
3491 typedef enum n_ia32_fisttp {
3492  n_ia32_fisttp_base = 0,
3493  n_ia32_fisttp_index = 1,
3494  n_ia32_fisttp_mem = 2,
3495  n_ia32_fisttp_val = 3,
3496 } n_ia32_fisttp;
3497 
3498 typedef enum pn_ia32_fld {
3499  pn_ia32_fld_res = 0,
3500  pn_ia32_fld_unused = 1,
3501  pn_ia32_fld_M = 2,
3502  pn_ia32_fld_X_regular = 3,
3503  pn_ia32_fld_X_except = 4,
3504 } pn_ia32_fld;
3505 
3506 typedef enum n_ia32_fld {
3507  n_ia32_fld_base = 0,
3508  n_ia32_fld_index = 1,
3509  n_ia32_fld_mem = 2,
3510 } n_ia32_fld;
3511 
3512 typedef enum pn_ia32_fld1 {
3513  pn_ia32_fld1_res = 0,
3514 } pn_ia32_fld1;
3515 
3516 typedef enum pn_ia32_fldl2e {
3517  pn_ia32_fldl2e_res = 0,
3518 } pn_ia32_fldl2e;
3519 
3520 typedef enum pn_ia32_fldl2t {
3521  pn_ia32_fldl2t_res = 0,
3522 } pn_ia32_fldl2t;
3523 
3524 typedef enum pn_ia32_fldlg2 {
3525  pn_ia32_fldlg2_res = 0,
3526 } pn_ia32_fldlg2;
3527 
3528 typedef enum pn_ia32_fldln2 {
3529  pn_ia32_fldln2_res = 0,
3530 } pn_ia32_fldln2;
3531 
3532 typedef enum pn_ia32_fldpi {
3533  pn_ia32_fldpi_res = 0,
3534 } pn_ia32_fldpi;
3535 
3536 typedef enum pn_ia32_fldz {
3537  pn_ia32_fldz_res = 0,
3538 } pn_ia32_fldz;
3539 
3540 typedef enum pn_ia32_fmul {
3541  pn_ia32_fmul_res = 0,
3542  pn_ia32_fmul_dummy = 1,
3543  pn_ia32_fmul_M = 2,
3544 } pn_ia32_fmul;
3545 
3546 typedef enum n_ia32_fmul {
3547  n_ia32_fmul_base = 0,
3548  n_ia32_fmul_index = 1,
3549  n_ia32_fmul_mem = 2,
3550  n_ia32_fmul_left = 3,
3551  n_ia32_fmul_right = 4,
3552  n_ia32_fmul_fpcw = 5,
3553 } n_ia32_fmul;
3554 
3555 typedef enum pn_ia32_fst {
3556  pn_ia32_fst_M = 0,
3557  pn_ia32_fst_X_regular = 1,
3558  pn_ia32_fst_X_except = 2,
3559 } pn_ia32_fst;
3560 
3561 typedef enum n_ia32_fst {
3562  n_ia32_fst_base = 0,
3563  n_ia32_fst_index = 1,
3564  n_ia32_fst_mem = 2,
3565  n_ia32_fst_val = 3,
3566 } n_ia32_fst;
3567 
3568 typedef enum pn_ia32_fstp {
3569  pn_ia32_fstp_M = 0,
3570  pn_ia32_fstp_X_regular = 1,
3571  pn_ia32_fstp_X_except = 2,
3572 } pn_ia32_fstp;
3573 
3574 typedef enum n_ia32_fstp {
3575  n_ia32_fstp_base = 0,
3576  n_ia32_fstp_index = 1,
3577  n_ia32_fstp_mem = 2,
3578  n_ia32_fstp_val = 3,
3579 } n_ia32_fstp;
3580 
3581 typedef enum pn_ia32_fsub {
3582  pn_ia32_fsub_res = 0,
3583  pn_ia32_fsub_dummy = 1,
3584  pn_ia32_fsub_M = 2,
3585 } pn_ia32_fsub;
3586 
3587 typedef enum n_ia32_fsub {
3588  n_ia32_fsub_base = 0,
3589  n_ia32_fsub_index = 1,
3590  n_ia32_fsub_mem = 2,
3591  n_ia32_fsub_left = 3,
3592  n_ia32_fsub_right = 4,
3593  n_ia32_fsub_fpcw = 5,
3594 } n_ia32_fsub;
3595 
3596 typedef enum n_ia32_l_Adc {
3597  n_ia32_l_Adc_left = 0,
3598  n_ia32_l_Adc_right = 1,
3599  n_ia32_l_Adc_eflags = 2,
3600 } n_ia32_l_Adc;
3601 
3602 typedef enum pn_ia32_l_Add {
3603  pn_ia32_l_Add_res = 0,
3604  pn_ia32_l_Add_flags = 1,
3605 } pn_ia32_l_Add;
3606 
3607 typedef enum n_ia32_l_Add {
3608  n_ia32_l_Add_left = 0,
3609  n_ia32_l_Add_right = 1,
3610 } n_ia32_l_Add;
3611 
3612 typedef enum pn_ia32_l_FloattoLL {
3613  pn_ia32_l_FloattoLL_res_high = 0,
3614  pn_ia32_l_FloattoLL_res_low = 1,
3615 } pn_ia32_l_FloattoLL;
3616 
3617 typedef enum n_ia32_l_FloattoLL {
3618  n_ia32_l_FloattoLL_val = 0,
3619 } n_ia32_l_FloattoLL;
3620 
3621 typedef enum pn_ia32_l_IMul {
3622  pn_ia32_l_IMul_res_low = 0,
3623  pn_ia32_l_IMul_flags = 1,
3624  pn_ia32_l_IMul_M = 2,
3625  pn_ia32_l_IMul_res_high = 3,
3626 } pn_ia32_l_IMul;
3627 
3628 typedef enum n_ia32_l_IMul {
3629  n_ia32_l_IMul_left = 0,
3630  n_ia32_l_IMul_right = 1,
3631 } n_ia32_l_IMul;
3632 
3633 typedef enum n_ia32_l_LLtoFloat {
3634  n_ia32_l_LLtoFloat_val_high = 0,
3635  n_ia32_l_LLtoFloat_val_low = 1,
3636 } n_ia32_l_LLtoFloat;
3637 
3638 typedef enum pn_ia32_l_Minus64 {
3639  pn_ia32_l_Minus64_res_low = 0,
3640  pn_ia32_l_Minus64_res_high = 1,
3641 } pn_ia32_l_Minus64;
3642 
3643 typedef enum n_ia32_l_Minus64 {
3644  n_ia32_l_Minus64_low = 0,
3645  n_ia32_l_Minus64_high = 1,
3646 } n_ia32_l_Minus64;
3647 
3648 typedef enum pn_ia32_l_Mul {
3649  pn_ia32_l_Mul_res_low = 0,
3650  pn_ia32_l_Mul_flags = 1,
3651  pn_ia32_l_Mul_M = 2,
3652  pn_ia32_l_Mul_res_high = 3,
3653 } pn_ia32_l_Mul;
3654 
3655 typedef enum n_ia32_l_Mul {
3656  n_ia32_l_Mul_left = 0,
3657  n_ia32_l_Mul_right = 1,
3658 } n_ia32_l_Mul;
3659 
3660 typedef enum n_ia32_l_Sbb {
3661  n_ia32_l_Sbb_minuend = 0,
3662  n_ia32_l_Sbb_subtrahend = 1,
3663  n_ia32_l_Sbb_eflags = 2,
3664 } n_ia32_l_Sbb;
3665 
3666 typedef enum pn_ia32_l_Sub {
3667  pn_ia32_l_Sub_res = 0,
3668  pn_ia32_l_Sub_flags = 1,
3669 } pn_ia32_l_Sub;
3670 
3671 typedef enum n_ia32_l_Sub {
3672  n_ia32_l_Sub_minuend = 0,
3673  n_ia32_l_Sub_subtrahend = 1,
3674 } n_ia32_l_Sub;
3675 
3676 typedef enum pn_ia32_xAdd {
3677  pn_ia32_xAdd_res = 0,
3678  pn_ia32_xAdd_flags = 1,
3679  pn_ia32_xAdd_M = 2,
3680 } pn_ia32_xAdd;
3681 
3682 typedef enum n_ia32_xAdd {
3683  n_ia32_xAdd_base = 0,
3684  n_ia32_xAdd_index = 1,
3685  n_ia32_xAdd_mem = 2,
3686  n_ia32_xAdd_left = 3,
3687  n_ia32_xAdd_right = 4,
3688 } n_ia32_xAdd;
3689 
3690 typedef enum pn_ia32_xAllOnes {
3691  pn_ia32_xAllOnes_res = 0,
3692 } pn_ia32_xAllOnes;
3693 
3694 typedef enum pn_ia32_xAnd {
3695  pn_ia32_xAnd_res = 0,
3696  pn_ia32_xAnd_flags = 1,
3697  pn_ia32_xAnd_M = 2,
3698 } pn_ia32_xAnd;
3699 
3700 typedef enum n_ia32_xAnd {
3701  n_ia32_xAnd_base = 0,
3702  n_ia32_xAnd_index = 1,
3703  n_ia32_xAnd_mem = 2,
3704  n_ia32_xAnd_left = 3,
3705  n_ia32_xAnd_right = 4,
3706 } n_ia32_xAnd;
3707 
3708 typedef enum pn_ia32_xAndNot {
3709  pn_ia32_xAndNot_res = 0,
3710  pn_ia32_xAndNot_flags = 1,
3711  pn_ia32_xAndNot_M = 2,
3712 } pn_ia32_xAndNot;
3713 
3714 typedef enum n_ia32_xAndNot {
3715  n_ia32_xAndNot_base = 0,
3716  n_ia32_xAndNot_index = 1,
3717  n_ia32_xAndNot_mem = 2,
3718  n_ia32_xAndNot_left = 3,
3719  n_ia32_xAndNot_right = 4,
3720 } n_ia32_xAndNot;
3721 
3722 typedef enum pn_ia32_xDiv {
3723  pn_ia32_xDiv_res = 0,
3724  pn_ia32_xDiv_flags = 1,
3725  pn_ia32_xDiv_M = 2,
3726 } pn_ia32_xDiv;
3727 
3728 typedef enum n_ia32_xDiv {
3729  n_ia32_xDiv_base = 0,
3730  n_ia32_xDiv_index = 1,
3731  n_ia32_xDiv_mem = 2,
3732  n_ia32_xDiv_left = 3,
3733  n_ia32_xDiv_right = 4,
3734 } n_ia32_xDiv;
3735 
3736 typedef enum pn_ia32_xLoad {
3737  pn_ia32_xLoad_res = 0,
3738  pn_ia32_xLoad_unused = 1,
3739  pn_ia32_xLoad_M = 2,
3740  pn_ia32_xLoad_X_regular = 3,
3741  pn_ia32_xLoad_X_except = 4,
3742 } pn_ia32_xLoad;
3743 
3744 typedef enum n_ia32_xLoad {
3745  n_ia32_xLoad_base = 0,
3746  n_ia32_xLoad_index = 1,
3747  n_ia32_xLoad_mem = 2,
3748 } n_ia32_xLoad;
3749 
3750 typedef enum pn_ia32_xMax {
3751  pn_ia32_xMax_res = 0,
3752  pn_ia32_xMax_flags = 1,
3753  pn_ia32_xMax_M = 2,
3754 } pn_ia32_xMax;
3755 
3756 typedef enum n_ia32_xMax {
3757  n_ia32_xMax_base = 0,
3758  n_ia32_xMax_index = 1,
3759  n_ia32_xMax_mem = 2,
3760  n_ia32_xMax_left = 3,
3761  n_ia32_xMax_right = 4,
3762 } n_ia32_xMax;
3763 
3764 typedef enum pn_ia32_xMin {
3765  pn_ia32_xMin_res = 0,
3766  pn_ia32_xMin_flags = 1,
3767  pn_ia32_xMin_M = 2,
3768 } pn_ia32_xMin;
3769 
3770 typedef enum n_ia32_xMin {
3771  n_ia32_xMin_base = 0,
3772  n_ia32_xMin_index = 1,
3773  n_ia32_xMin_mem = 2,
3774  n_ia32_xMin_left = 3,
3775  n_ia32_xMin_right = 4,
3776 } n_ia32_xMin;
3777 
3778 typedef enum pn_ia32_xMul {
3779  pn_ia32_xMul_res = 0,
3780  pn_ia32_xMul_flags = 1,
3781  pn_ia32_xMul_M = 2,
3782 } pn_ia32_xMul;
3783 
3784 typedef enum n_ia32_xMul {
3785  n_ia32_xMul_base = 0,
3786  n_ia32_xMul_index = 1,
3787  n_ia32_xMul_mem = 2,
3788  n_ia32_xMul_left = 3,
3789  n_ia32_xMul_right = 4,
3790 } n_ia32_xMul;
3791 
3792 typedef enum pn_ia32_xOr {
3793  pn_ia32_xOr_res = 0,
3794  pn_ia32_xOr_flags = 1,
3795  pn_ia32_xOr_M = 2,
3796 } pn_ia32_xOr;
3797 
3798 typedef enum n_ia32_xOr {
3799  n_ia32_xOr_base = 0,
3800  n_ia32_xOr_index = 1,
3801  n_ia32_xOr_mem = 2,
3802  n_ia32_xOr_left = 3,
3803  n_ia32_xOr_right = 4,
3804 } n_ia32_xOr;
3805 
3806 typedef enum pn_ia32_xPzero {
3807  pn_ia32_xPzero_res = 0,
3808 } pn_ia32_xPzero;
3809 
3810 typedef enum pn_ia32_xStore {
3811  pn_ia32_xStore_M = 0,
3812  pn_ia32_xStore_X_regular = 1,
3813  pn_ia32_xStore_X_except = 2,
3814 } pn_ia32_xStore;
3815 
3816 typedef enum n_ia32_xStore {
3817  n_ia32_xStore_base = 0,
3818  n_ia32_xStore_index = 1,
3819  n_ia32_xStore_mem = 2,
3820  n_ia32_xStore_val = 3,
3821 } n_ia32_xStore;
3822 
3823 typedef enum pn_ia32_xSub {
3824  pn_ia32_xSub_res = 0,
3825  pn_ia32_xSub_flags = 1,
3826  pn_ia32_xSub_M = 2,
3827 } pn_ia32_xSub;
3828 
3829 typedef enum n_ia32_xSub {
3830  n_ia32_xSub_base = 0,
3831  n_ia32_xSub_index = 1,
3832  n_ia32_xSub_mem = 2,
3833  n_ia32_xSub_minuend = 3,
3834  n_ia32_xSub_subtrahend = 4,
3835 } n_ia32_xSub;
3836 
3837 typedef enum pn_ia32_xUnknown {
3838  pn_ia32_xUnknown_res = 0,
3839 } pn_ia32_xUnknown;
3840 
3841 typedef enum pn_ia32_xXor {
3842  pn_ia32_xXor_res = 0,
3843  pn_ia32_xXor_flags = 1,
3844  pn_ia32_xXor_M = 2,
3845 } pn_ia32_xXor;
3846 
3847 typedef enum n_ia32_xXor {
3848  n_ia32_xXor_base = 0,
3849  n_ia32_xXor_index = 1,
3850  n_ia32_xXor_mem = 2,
3851  n_ia32_xXor_left = 3,
3852  n_ia32_xXor_right = 4,
3853 } n_ia32_xXor;
3854 
3855 typedef enum pn_ia32_xZero {
3856  pn_ia32_xZero_res = 0,
3857 } pn_ia32_xZero;
3858 
3859 typedef enum pn_ia32_xxLoad {
3860  pn_ia32_xxLoad_res = 0,
3861  pn_ia32_xxLoad_M = 1,
3862  pn_ia32_xxLoad_X_regular = 2,
3863  pn_ia32_xxLoad_X_except = 3,
3864 } pn_ia32_xxLoad;
3865 
3866 typedef enum n_ia32_xxLoad {
3867  n_ia32_xxLoad_base = 0,
3868  n_ia32_xxLoad_index = 1,
3869  n_ia32_xxLoad_mem = 2,
3870 } n_ia32_xxLoad;
3871 
3872 typedef enum pn_ia32_xxStore {
3873  pn_ia32_xxStore_M = 0,
3874  pn_ia32_xxStore_X_regular = 1,
3875  pn_ia32_xxStore_X_except = 2,
3876 } pn_ia32_xxStore;
3877 
3878 typedef enum n_ia32_xxStore {
3879  n_ia32_xxStore_base = 0,
3880  n_ia32_xxStore_index = 1,
3881  n_ia32_xxStore_mem = 2,
3882  n_ia32_xxStore_val = 3,
3883 } n_ia32_xxStore;
3884 
3885 
3886 #endif
ir_type
struct ir_type ir_type
Type.
Definition: firm_types.h:71
dbg_info
struct dbg_info dbg_info
Source Reference.
Definition: firm_types.h:40
ir_switch_table
struct ir_switch_table ir_switch_table
A switch table mapping integer numbers to proj-numbers of a Switch-node.
Definition: firm_types.h:102
get_irn_op
ir_op * get_irn_op(const ir_node *node)
Returns the opcode struct of the node.
ir_op
struct ir_op ir_op
Node Opcode.
Definition: firm_types.h:56
ir_entity
struct ir_entity ir_entity
Entity.
Definition: firm_types.h:83
ir_mode
struct ir_mode ir_mode
SSA Value mode.
Definition: firm_types.h:59
ir_node
struct ir_node ir_node
Procedure Graph Node.
Definition: firm_types.h:53
smaller_mode
int smaller_mode(const ir_mode *sm, const ir_mode *lm)
Returns true if a value of mode sm can be converted to mode lm without loss.